Abstract: A liquid crystal display device is provided which includes a substrate, a plurality of scan lines on the substrate and a scan driver IC on the substrate. The scan driver IC includes a plurality of scan line selectors, each scan line selector including a first input terminal for receiving a set signal, a second input terminal for receiving a scan reset signal, a shift input terminal for receiving a shift signal, a shift reset terminal for receiving a shift reset signal, a first output terminal connected respectively to one of the plurality of scan lines for outputting a scan line selection signal in accordance with the set signal and the scan reset signal, and a shift output terminal for outputting a shift signal in accordance with the set signal and the shift reset signal.

Abstract: A liquid crystal display is provided which includes a substrate, a plurality of scan lines on the substrate and a scan driver IC on the substrate. The scan driver IC includes a plurality of row selectors and each row selector includes a first input terminal for receiving a set signal, a second input terminal for receiving a reset signal, a third input terminal for receiving a shift signal, and an output terminal connected respectively to one of the plurality of scan lines to apply a driving signal according to the set signal and the reset signal.

Abstract: Disclosed is an improved gate line driver and method for a liquid crystal display. The method includes: receiving a horizontal synchronous Fh signal; and producing at least two non-overlapping gate line pulses during each period of the Fh signal. A first way to produce the gate line pulses is to: produce a gate shift clock GSC signal having a frequency f(GSC) at least twice as great as the frequency of the Fh signal f(Fh) such that f(GSC).gtoreq.f(Fh); and provide one gate line pulse during each period of the GSC signal. A second way to produce the gate line pulses is to: produce a gate shift clock GSC signal having a frequency f(GSC) the same as the frequency of the Fh signal f(Fh) such that f(GSC)=f(Fh); move a pulse through a plurality of shift registers according to the GSC signal; logically combine, e.g., by ANDing, the GSC signal and the sequence of shift register pulses to provide one of the gate line pulses during each period of the Fh signal; and logically combine, e.g.