Patents by Inventor Ki-Seog Youn

Ki-Seog Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7795110
    Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: September 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
  • Patent number: 7709340
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Patent number: 7557415
    Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: July 7, 2009
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-jong Roh, Hye-kyoung Lee
  • Publication number: 20090051014
    Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.
    Type: Application
    Filed: October 15, 2008
    Publication date: February 26, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Su-gon Bae
  • Publication number: 20080188057
    Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 7, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Deok-Hyung Lee, Sung-Gun Kang, Kong-Soo Cheong
  • Patent number: 7364987
    Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Hee-Sung Kang, Tae-Woong Kang
  • Patent number: 7358588
    Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: April 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
  • Publication number: 20070293045
    Abstract: A semiconductor device may include a semiconductor substrate having a trench, a device isolation layer filling the trench, and a liner nitride layer disposed between the semiconductor substrate and the device isolation layer. The device isolation layer may additionally cover a portion of the substrate surrounding the trench. The liner nitride layer may have an upper portion and a lower portion, wherein the upper portion may be thinner than the lower portion. The liner nitride layer may reduce or prevent a recess from being generated between an active region and a device isolation region. Accordingly, a relatively high-quality semiconductor device may be fabricated using a simplified process.
    Type: Application
    Filed: June 14, 2007
    Publication date: December 20, 2007
    Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Joo-Hyoung Lee, Kwang-Duk Kim
  • Publication number: 20070187770
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 16, 2007
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Publication number: 20070164391
    Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 19, 2007
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-Jong Roh, Hye-Kyoung Lee
  • Patent number: 7094694
    Abstract: In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: August 22, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kong-Soo Cheong, Ki-Seog Youn, Kyung-Soo Kim
  • Publication number: 20060163669
    Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.
    Type: Application
    Filed: January 17, 2006
    Publication date: July 27, 2006
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Su-gon Bae
  • Publication number: 20060128114
    Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
    Type: Application
    Filed: December 13, 2005
    Publication date: June 15, 2006
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
  • Publication number: 20050158984
    Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 21, 2005
    Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Hee-Sung Kang, Tae-Woong Kang
  • Publication number: 20050142779
    Abstract: In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 30, 2005
    Inventors: Kong-Soo Cheong, Ki-Seog Youn, Kyung-Soo Kim
  • Patent number: 6100164
    Abstract: A semiconductor device and a method of fabricating the same are disclosed. The method includes the steps of forming an anti-oxidation layer on a substrate, forming an oxidizable layer on portions of the anti-oxidation layer to expose a portion of the anti-oxidation layer, varying a size of the exposed portion of the anti-oxidation layer by oxidizing at least a portion of the oxidizable layer, and forming a trench in the substrate according to the size of the exposed portion of the anti-oxidation layer. The semiconductor device includes an anti-oxidation layer formed on a substrate an oxidation layer formed on portions of the anti-oxidation layer by oxidizing at least a portion of an oxidizable layer, so as to define an isolation region of the semiconductor device, a trench formed in the substrate using the oxidation layer, and a field oxide layer formed in the trench.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: August 8, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventors: Kang-Sik Youn, Ki-Seog Youn, Ku-Chul Joung