Patents by Inventor Ki-Seog Youn
Ki-Seog Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7795110Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.Type: GrantFiled: February 21, 2008Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
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Patent number: 7709340Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.Type: GrantFiled: February 12, 2007Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
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Patent number: 7557415Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.Type: GrantFiled: January 8, 2007Date of Patent: July 7, 2009Assignee: Samsung Electroncis Co., Ltd.Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-jong Roh, Hye-kyoung Lee
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Publication number: 20090051014Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.Type: ApplicationFiled: October 15, 2008Publication date: February 26, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-seog Youn, Jong-hyon Ahn, Su-gon Bae
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Publication number: 20080188057Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.Type: ApplicationFiled: February 21, 2008Publication date: August 7, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Deok-Hyung Lee, Sung-Gun Kang, Kong-Soo Cheong
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Patent number: 7364987Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.Type: GrantFiled: January 14, 2005Date of Patent: April 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Hee-Sung Kang, Tae-Woong Kang
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Patent number: 7358588Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.Type: GrantFiled: December 13, 2005Date of Patent: April 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
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Publication number: 20070293045Abstract: A semiconductor device may include a semiconductor substrate having a trench, a device isolation layer filling the trench, and a liner nitride layer disposed between the semiconductor substrate and the device isolation layer. The device isolation layer may additionally cover a portion of the substrate surrounding the trench. The liner nitride layer may have an upper portion and a lower portion, wherein the upper portion may be thinner than the lower portion. The liner nitride layer may reduce or prevent a recess from being generated between an active region and a device isolation region. Accordingly, a relatively high-quality semiconductor device may be fabricated using a simplified process.Type: ApplicationFiled: June 14, 2007Publication date: December 20, 2007Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Joo-Hyoung Lee, Kwang-Duk Kim
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Publication number: 20070187770Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.Type: ApplicationFiled: February 12, 2007Publication date: August 16, 2007Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
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Publication number: 20070164391Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.Type: ApplicationFiled: January 8, 2007Publication date: July 19, 2007Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-Jong Roh, Hye-Kyoung Lee
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Patent number: 7094694Abstract: In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.Type: GrantFiled: December 29, 2004Date of Patent: August 22, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Kong-Soo Cheong, Ki-Seog Youn, Kyung-Soo Kim
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Publication number: 20060163669Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.Type: ApplicationFiled: January 17, 2006Publication date: July 27, 2006Inventors: Ki-seog Youn, Jong-hyon Ahn, Su-gon Bae
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Publication number: 20060128114Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.Type: ApplicationFiled: December 13, 2005Publication date: June 15, 2006Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
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Publication number: 20050158984Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.Type: ApplicationFiled: January 14, 2005Publication date: July 21, 2005Inventors: Ki-Seog Youn, Jong-Hyon Ahn, Hee-Sung Kang, Tae-Woong Kang
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Publication number: 20050142779Abstract: In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.Type: ApplicationFiled: December 29, 2004Publication date: June 30, 2005Inventors: Kong-Soo Cheong, Ki-Seog Youn, Kyung-Soo Kim
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Patent number: 6100164Abstract: A semiconductor device and a method of fabricating the same are disclosed. The method includes the steps of forming an anti-oxidation layer on a substrate, forming an oxidizable layer on portions of the anti-oxidation layer to expose a portion of the anti-oxidation layer, varying a size of the exposed portion of the anti-oxidation layer by oxidizing at least a portion of the oxidizable layer, and forming a trench in the substrate according to the size of the exposed portion of the anti-oxidation layer. The semiconductor device includes an anti-oxidation layer formed on a substrate an oxidation layer formed on portions of the anti-oxidation layer by oxidizing at least a portion of an oxidizable layer, so as to define an isolation region of the semiconductor device, a trench formed in the substrate using the oxidation layer, and a field oxide layer formed in the trench.Type: GrantFiled: December 15, 1997Date of Patent: August 8, 2000Assignee: LG Semicon Co., Ltd.Inventors: Kang-Sik Youn, Ki-Seog Youn, Ku-Chul Joung