Patents by Inventor Ki-Seok Oh
Ki-Seok Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11797203Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: GrantFiled: September 6, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu Choi, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
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Patent number: 11790963Abstract: An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.Type: GrantFiled: March 30, 2022Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ki-Seok Oh
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Publication number: 20230317138Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Patent number: 11749337Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: June 16, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Patent number: 11749338Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: July 29, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Publication number: 20230273668Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.Type: ApplicationFiled: May 9, 2023Publication date: August 31, 2023Inventor: Ki-Seok OH
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Publication number: 20230274776Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: May 9, 2023Publication date: August 31, 2023Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Patent number: 11733890Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: GrantFiled: September 6, 2022Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu Choi, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
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Patent number: 11662799Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.Type: GrantFiled: May 13, 2020Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ki-Seok Oh
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Patent number: 11644989Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: GrantFiled: July 27, 2020Date of Patent: May 9, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu Choi, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
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Publication number: 20230066632Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.Type: ApplicationFiled: October 18, 2022Publication date: March 2, 2023Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
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Publication number: 20230044654Abstract: An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.Type: ApplicationFiled: March 30, 2022Publication date: February 9, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: KI-SEOK OH
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Publication number: 20230004313Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: ApplicationFiled: September 6, 2022Publication date: January 5, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu CHOI, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
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Publication number: 20220413725Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: ApplicationFiled: September 6, 2022Publication date: December 29, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu CHOI, Ki-seok OH, Seung-jun SHIN, Hye-ran KIM
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Publication number: 20220383931Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Patent number: 11508420Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.Type: GrantFiled: June 23, 2021Date of Patent: November 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
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Patent number: 11481149Abstract: A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.Type: GrantFiled: December 6, 2019Date of Patent: October 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Young Lim, Ki-Seok Oh, Sungyong Seo, Youngjin Cho, Insu Choi
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Patent number: 11423971Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: December 29, 2021Date of Patent: August 23, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Patent number: 11393522Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: January 14, 2021Date of Patent: July 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Publication number: 20220122648Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: December 29, 2021Publication date: April 21, 2022Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN