Patents by Inventor Ki-Seon Park
Ki-Seon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140368Abstract: Provided are a vehicle sensor cleaning apparatus and a control method thereof. The vehicle sensor cleaning apparatus includes a liquid sprayer configured to spray washer fluid on at least one sensor arranged in a vehicle, an air sprayer configured to spray air on the at least one sensor, a liquid controller configured to control washer fluid spraying of the liquid sprayer, and an air controller configured to control air spraying of the air sprayer.Type: ApplicationFiled: October 25, 2023Publication date: May 2, 2024Applicants: DY AUTO Corporation, DY-ESSYS Corp.Inventors: Jong Wook Lee, Sin Won Kang, Seong Jun Kim, Kyung Seon Min, Gyu Seon Lee, Jong Hyun Jin, Min Wook Park, Je Min Mun, Sun Ju Kim, Ki Chan Lee
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Patent number: 11245070Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.Type: GrantFiled: May 30, 2019Date of Patent: February 8, 2022Assignee: SK hynix Inc.Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
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Patent number: 10777742Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: GrantFiled: November 25, 2019Date of Patent: September 15, 2020Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Publication number: 20200098984Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Patent number: 10559422Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; forming an initial spacer containing a metal over the variable resistance element; performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.Type: GrantFiled: April 7, 2017Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin, Jeong-Myeong Kim, Bo-Kyung Jung
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Patent number: 10490741Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: GrantFiled: November 16, 2016Date of Patent: November 26, 2019Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Publication number: 20190280199Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.Type: ApplicationFiled: May 30, 2019Publication date: September 12, 2019Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
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Patent number: 10367137Abstract: Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.Type: GrantFiled: March 24, 2017Date of Patent: July 30, 2019Assignee: SK hynix Inc.Inventors: Guk-Cheon Kim, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Yang-Kon Kim
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Patent number: 10333061Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.Type: GrantFiled: September 13, 2017Date of Patent: June 25, 2019Assignee: SK hynix Inc.Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
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Patent number: 10333060Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.Type: GrantFiled: August 15, 2017Date of Patent: June 25, 2019Assignee: SK hynix Inc.Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
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Patent number: 10305030Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: GrantFiled: January 8, 2018Date of Patent: May 28, 2019Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Publication number: 20190079873Abstract: An electronic device includes semiconductor memory, the semiconductor memory including an under layer; a first magnetic layer located over the under layer and having a variable magnetization direction; a tunnel barrier layer located over the first magnetic layer; and a second magnetic layer located over the tunnel barrier layer and having a pinned magnetization direction, wherein the under layer includes a first metal nitride layer having a NaCl crystal structure and a second metal nitride layer containing a light metal.Type: ApplicationFiled: November 9, 2018Publication date: March 14, 2019Inventors: Yang-Kon KIM, Ki-Seon PARK, Bo-Mi LEE, Won-Joon CHOI, Guk-Cheon KIM, Daisuke WATANABE, Makoto NAGAMINE, Young-Min EEH, Koji UEDA, Toshihiko NAGASE, Kazuya SAWADA
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Publication number: 20190067565Abstract: An electronic device including a semiconductor memory is provided to include a predetermined structure; and a hard mask pattern disposed over the predetermined structure and including a sputtering carbon layer as a permanent part of the semiconductor memory.Type: ApplicationFiled: May 31, 2018Publication date: February 28, 2019Inventors: Ga-Young Ha, Ki-Seon Park
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Patent number: 10120799Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.Type: GrantFiled: August 11, 2017Date of Patent: November 6, 2018Assignee: SK hynix Inc.Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
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Publication number: 20180182956Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.Type: ApplicationFiled: September 13, 2017Publication date: June 28, 2018Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
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Patent number: 9991313Abstract: According to one embodiment, a magnetic memory includes a first magnetic layer, a second magnetic layer, a non-magnetic intermediate layer provided between the first magnetic layer and the second magnetic layer and an underlying layer provided on an opposite side of the first magnetic layer with respect to the intermediate layer, and the underlying layer contains AlN of a hcp structure.Type: GrantFiled: March 12, 2015Date of Patent: June 5, 2018Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.Inventors: Daisuke Watanabe, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Yang Kon Kim, Bo Mi Lee, Guk Cheon Kim, Won Joon Choi, Ki Seon Park
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Publication number: 20180130945Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Publication number: 20180123030Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.Type: ApplicationFiled: August 15, 2017Publication date: May 3, 2018Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
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Publication number: 20180114639Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; forming an initial spacer containing a metal over the variable resistance element; performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.Type: ApplicationFiled: April 7, 2017Publication date: April 26, 2018Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin, Jeong-Myeong Kim, Bo-Kyung Jung
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Patent number: 9910596Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate and having a contact hole; a contact plug formed in a lower part of the contact hole; a contact pad formed in an upper part of the contact hole; an amorphous buffer layer interposed between the contact plug and the contact pad; and a variable resistance element formed over the contact pad.Type: GrantFiled: May 11, 2016Date of Patent: March 6, 2018Assignee: SK hynix Inc.Inventors: Chi-Ho Kim, Ki-Seon Park