Abstract: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

Abstract: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Abstract: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Abstract: A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.

Abstract: A semiconductor device having reduced pitting may be formed from isolation layer patterns on a semiconductor substrate defining an active region, a tunnel oxide layer on the active region, the tunnel oxide layer having a nitrified surface, a floating gate on the tunnel oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer.

Abstract: Methods of forming a gate structure of a non-volatile memory device include forming a gate pattern having a control gate on a semiconductor substrate. An oxidation-preventing layer is formed on the control gate in a process chamber while maintaining a substantially oxygen free atmosphere in the process chamber. An oxide spacer is formed on a sidewall of the gate pattern with the oxidation-preventing layer thereon in the process chamber. Forming an oxidation-preventing layer may include exposing the gate pattern to a first gas in the process chamber and forming an oxide spacer may include exposing the gate pattern to a second gas including oxygen in the process chamber.

Abstract: A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.

Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

Abstract: Methods of forming a gate structure of a non-volatile memory device include forming a gate pattern having a control gate on a semiconductor substrate. An oxidation-preventing layer is formed on the control gate in a process chamber while maintaining a substantially oxygen free atmosphere in the process chamber. An oxide spacer is formed on a sidewall of the gate pattern with the oxidation-preventing layer thereon in the process chamber. Forming an oxidation-preventing layer may include exposing the gate pattern to a first gas in the process chamber and forming an oxide spacer may include exposing the gate pattern to a second gas including oxygen in the process chamber.

Abstract: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Abstract: A method of forming a dielectric layer having a reduced thickness according to embodiments of the invention includes forming a lower oxide layer on a substrate, and forming a nitride layer on the lower oxide layer. Then, a preliminary oxide layer is formed on the nitride layer. A radical oxidation process using oxygen radicals is performed on the preliminary oxide layer to form an upper oxide layer on the nitride layer. The dielectric layer includes an ONO composite layer consisting of the lower oxide layer, the nitride layer, and the upper oxide layer. Due to the decreased thickness of the dielectric layer, the dielectric layer has an improved capacitance and an increased coupling coefficient.

Abstract: A method for forming a capacitor comprises forming a supporting insulating film, an etching stopper film made of alumina series or hafnium oxide series, and a mold insulating film on a surface of a semiconductor substrate having a first structure including conductive plugs surrounded by a first insulating film, patterning the mold insulating film, the etching stopper film and the supporting insulating film to form openings that expose the conductive plugs, forming a storage node conductive film electrically connected to the conductive plugs on the surface of the semiconductor substrate having the openings formed therein and concurrently annealing the etching stopper film, separating the storage node conductive film to form a plurality of storage nodes, exposing at least a part of an outer surface of the storage node by selectively etching remaining mold insulating film, which is exposed by the separated storage node conductive film, until the etching stopper film is exposed, and forming a plurality of plate n

Abstract: A method of forming a dielectric layer for a non-volatile memory cell is disclosed. According to the method, a dielectric layer is formed by successively forming a lower oxide layer, a nitride layer and an upper oxide layer on a semiconductor substrate. The lower and upper oxide layers are formed using a radical oxidation process. A method of forming a non-volatile memory cell having the dielectric layer is also disclosed.