Abstract: The present disclosure relates to a display device including: a substrate having a rounded corner; a plurality of pixels disposed on the substrate; and a light blocking member disposed on a corner of the substrate and overlapping at least part of a first pixel of the plurality of pixels, the first pixel disposed at the rounded corner, wherein the first pixel is configured to generate a lower luminance, the lower luminance referring to a luminance lower than a normal luminance.

Abstract: A timing controller includes a plurality of image enhancement blocks, a plurality of dithering blocks and a random number generating block. The plurality of image enhancement blocks performs image quality enhancement operations for input image data. The plurality of dithering blocks performs random dithering operations for outputs of the plurality of image enhancement blocks based on a plurality of random number tables. The random number generating block generates the plurality of random number tables which is provided to the plurality of dithering blocks.

Abstract: A display apparatus includes a display panel comprising a plurality of gate lines and a plurality of data lines, a gate driver circuit configured to generate a plurality of gate signals sequentially applied to the gate lines, and a timing controller configured to generate a reference control signal, the reference control signal adjusting at least one of a pulse-width and a phase of a predetermined gate signal among the gate signals.

Abstract: The present disclosure relates to a display device including: a substrate having a rounded corner; a plurality of pixels disposed on the substrate; and a light blocking member disposed on a corner of the substrate and overlapping at least part of a first pixel of the plurality of pixels, the first pixel disposed at the rounded corner, wherein the first pixel is configured to generate a lower luminance, the lower luminance referring to a luminance lower than a normal luminance.

Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: A display apparatus including a classifier configured to classify image data into preset data of an n-bits (“n” is a natural number), a toggle counter configured to count a number of toggles based on preset data of a present horizontal line and a previous horizontal line and to calculate a final toggle number using a weighted values corresponding to a swing width between data voltages of the present and previous horizontal lines, a determiner configured to determine a representative toggle number of a present frame based on a plurality of final toggle numbers of the present frame, compare the representative toggle number with a plurality of threshold values and determine a level of a power control signal based on a compared result.

Abstract: An I2C router system includes an I2C router part, a first slave device and a second slave device. The I2C router part includes a first I2C router configured to output a first I2C signal via a first I2C bus, and a second I2C router configured to output a second I2C signal via a second I2C bus. The first slave device can be configured to receive the first I2C signal via the first I2C bus. The second slave device can be configured to receive the second I2C signal via the second I2C bus.

Abstract: A timing controller includes a plurality of image enhancement blocks, a plurality of dithering blocks and a random number generating block. The plurality of image enhancement blocks performs image quality enhancement operations for input image data. The plurality of dithering blocks performs random dithering operations for outputs of the plurality of image enhancement blocks based on a plurality of random number tables. The random number generating block generates the plurality of random number tables which is provided to the plurality of dithering blocks.

Abstract: A display apparatus includes a display panel comprising a plurality of gate lines and a plurality of data lines, a gate driver circuit configured to generate a plurality of gate signals sequentially applied to the gate lines, and a timing controller configured to generate a reference control signal, the reference control signal adjusting at least one of a pulse-width and a phase of a predetermined gate signal among the gate signals.

Abstract: A display apparatus including a classifier configured to classify image data into preset data of an n-bits (“n” is a natural number), a toggle counter configured to count a number of toggles based on preset data of a present horizontal line and a previous horizontal line and to calculate a final toggle number using a weighted values corresponding to a swing width between data voltages of the present and previous horizontal lines, a determiner configured to determine a representative toggle number of a present frame based on a plurality of final toggle numbers of the present frame, compare the representative toggle number with a plurality of threshold values and determine a level of a power control signal based on a compared result.

Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: An I2C router system includes an I2C router part, a first slave device and a second slave device. The I2C router part includes a first I2C router configured to output a first I2C signal via a first I2C bus, and a second I2C router configured to output a second I2C signal via a second I2C bus. The first slave device can be configured to receive the first I2C signal via the first I2C bus. The second slave device can be configured to receive the second I2C signal via the second I2C bus.