Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a drift region disposed in a surface portion of a substrate, a body region disposed on one side of the drift region, a gate structure disposed on a portion of the drift region and a portion of the body region, a source region disposed in a surface portion of the body region to be adjacent to the gate structure, a drain region disposed in a surface portion of the drift region to be spaced apart from the gate structure, an insulating layer pattern disposed on a portion of the gate structure and a second surface portion of the drift region between the gate structure and the drain region, and a floating electrode disposed on the insulating layer pattern to reduce an electric field in the drift region.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on a substrate. (2) Forming an etch stop film on/over the lower electrode pattern. (3) Forming a first interlayer insulating layer on/over the etch stop film. (4) Forming an upper electrode pattern on/over the first interlayer insulating layer. (5) Forming a second interlayer insulating layer on/over the upper electrode pattern. (6) Forming an etch blocking layer positioned between the lower electrode pattern and the upper electrode pattern which passes through the second interlayer insulating layer and the first interlayer insulating layer. (7) Forming a cavity which exposes a side of the etch blocking layer by etching the second interlayer insulating layer and the first interlayer insulating layer. (8) Forming a contact ball in the cavity.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on a substrate. (2) Forming an etch stop film on/over the lower electrode pattern. (3) Forming a first interlayer insulating layer on/over the etch stop film. (4) Forming an upper electrode pattern on/over the first interlayer insulating layer. (5) Forming a second interlayer insulating layer on/over the upper electrode pattern. (6) Forming an etch blocking layer positioned between the lower electrode pattern and the upper electrode pattern which passes through the second interlayer insulating layer and the first interlayer insulating layer. (7) Forming a cavity which exposes a side of the etch blocking layer by etching the second interlayer insulating layer and the first interlayer insulating layer. (8) Forming a contact ball in the cavity.

Abstract: A stack capacitor in a semiconductor device includes a first capacitor formed on and/or over a semiconductor substrate and a second capacitor formed on and/or over the first capacitor. The first and second capacitors each have a multi-layer laminated structure which includes a lower electrode, a capacitor dielectric layer and an upper electrode. At least two of the lower electrodes and the upper electrodes are arranged vertically with respect to each other to have the same width and/or surface area.

Abstract: A semiconductor device according to an embodiment includes device isolating layers having a top surface lower than a sheet height of a semiconductor substrate; a gate insulating layer and a gate electrode sequentially stacked on the upper surface of an active region of the semiconductor substrate between the device isolating layers; a spacer formed at the side wall of the gate electrode; a source/drain region formed in the semiconductor substrate between the spacer and the device isolating layers; and a silicide film formed on the source/drain region.

Abstract: A lateral MOS transistor that can include a first device isolating layer formed in a semiconductor substrate; a second device isolating layer formed in the semiconductor substrate, the second device isolation layer having a different width than the first device isolation layer and also having an etched groove provided therein; a gate insulating layer formed in the etched groove; a gate electrode formed over the gate insulating layer; and a source/drain region horizontally arranged in the semiconductor substrate adjacent to the gate electrode.

Abstract: A stack capacitor in a semiconductor device includes a first capacitor formed on and/or over a semiconductor substrate and a second capacitor formed on and/or over the first capacitor. The first and second capacitors each have a multi-layer laminated structure which includes a lower electrode, a capacitor dielectric layer and an upper electrode. At least two of the lower electrodes and the upper electrodes are arranged vertically with respect to each other to have the same width and/or surface area.

Abstract: A lateral MOS transistor that can include a first device isolating layer formed in a semiconductor substrate; a second device isolating layer formed in the semiconductor substrate, the second device isolation layer having a different width than the first device isolation layer and also having an etched groove provided therein; a gate insulating layer formed in the etched groove; a gate electrode formed over the gate insulating layer; and a source/drain region horizontally arranged in the semiconductor substrate adjacent to the gate electrode.

Abstract: A semiconductor device according to an embodiment includes device isolating layers having a top surface lower than a sheet height of a semiconductor substrate; a gate insulating layer and a gate electrode sequentially stacked on the upper surface of an active region of the semiconductor substrate between the device isolating layers; a spacer formed at the side wall of the gate electrode; a source/drain region formed in the semiconductor substrate between the spacer and the device isolating layers; and a silicide film formed on the source/drain region.

Abstract: A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×1012˜1.5×1013atoms/cm2 performed at an energy level of 10˜100keV.

Abstract: A method of fabricating a semiconductor device is provided, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a transistor channel area. The method includes forming a gate insulating layer on a semiconductor substrate, forming a channel ion area in the substrate, forming a gate electrode on the gate insulating layer, forming a sidewall insulating layer on the gate electrode, forming lightly doped regions in the substrate adjacent to the channel ion area and aligned with the gate electrode, forming a spacer insulating layer on the sidewall insulating layer, forming spacers on sidewalls of the gate electrode, and forming heavily doped regions in the substrate aligned with the spacer.