Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A semiconductor package and method of manufacture has a substrate having an aperture. A semiconductor die is positioned in the aperture of the substrate and attached to a heat spreader by a first adhesive and electrically coupled to the substrate by at least one conductive wire. The heat spreader spans the aperture and is peripherally attached to a bottom surface of the substrate by a second adhesive. An encapsulant encapsulates the aperture, the semiconductor die, and the electrically conductive wire.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A semiconductor package comprises a plurality of stacked semiconductor chips having the same structure. Therefore, the semiconductor chips can be produced using masks of the same design, resulting in a reduction in production cost and an improvement in productivity. Each of the semiconductor chips includes a plurality of through-silicon vias penetrating therethrough. The through-silicon vias of each semiconductor chip include at least one signal pad through which a common signal is delivered to the semiconductor chip and at least one chip enable pad connected to at least one chip enable pin to select the semiconductor chip. The chip enable pin may be connected to or disconnected from the chip enable pad through a conductive line to select the semiconductor chip. The conductive line is sawn to disconnect the chip enable pin from the chip enable pad before stacking of the semiconductor chip.

Abstract: Semiconductor devices are disclosed. In an embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die. The stack of the second semiconductor dies is encapsulated by an encapsulant. Redistribution layers are formed on one surface of the stack and are connected to the through-silicon vias. Solder balls are attached to the respective redistribution layers. In another embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die formed with through-silicon vias. Redistribution layers are formed on the back surface of the first semiconductor die. Solder balls are attached to the respective redistribution layers. Further disclosed are methods for fabricating the semiconductor devices.

Abstract: Disclosed is a controller of a grid coupled type doubly-fed induction generator having a multi-level converter topology, which can control the doubly-fed induction generator having a high voltage specification and can perform a fault ride-through function, an anti-islanding function and a grid voltage synchronization function required for a dispersed power generation facility. The controller makes a H-bridge multi-level converter generate a three-phase voltage waveform resulted from the structure that single-phase converters each being composed of a 2-leg IGBT are stacked in a serial manner, and controls a rotor current so as to make the rotor coil of the doubly-fed induction generator in charge of a slip power only. The boost converter is composed of a 3-leg IGBT and a boost inductor generating a direct current voltage of its source required for the H-bridge multi-level converter.

Abstract: Disclosed herein is an electric power converting device and power converting method for controlling doubly-fed induction generators, which provides a synchronous generator for generating auxiliary electric power independently of a doubly-fed induction generator so as to generate electricity even in a system power-free environment, a grid-side converter is composed of a three-phase four-wire converter so as to generate a balanced voltage even in an unbalanced load condition and automatically synchronize a stator voltage of a doubly-fed induction generator and a system voltage with each other.

Abstract: A semiconductor package has a substrate having a first surface, a second surface, and a through hole opening. A heat spreader has a first surface, a second surface, and a plurality of notches formed on the second surface. A semiconductor die is coupled to the first surface of the heat spreader. The semiconductor die is electrically coupled to the substrate. An encapsulant is used to cover portions of the first surface of the substrate, portions of the first surface of the heat spreader, and the semiconductor die. A first set of solder balls is coupled to the second surface of the substrate. A second set of solder balls is coupled to the second surface of the heat spreader wherein the second set of solder balls is located in the notches.

Abstract: Disclosed is a controller of a grid coupled type doubly-fed induction generator having a multi-level converter topology, which can control the doubly-fed induction generator having a high voltage specification and can perform a fault ride-through function, an anti-islanding function and a grid voltage synchronization function required for a dispersed power generation facility. The controller makes a H-bridge multi-level converter generate a three-phase voltage waveform resulted from the structure that single-phase converters each being composed of a 2-leg IGBT are stacked in a serial manner, and controls a rotor current so as to make the rotor coil of the doubly-fed induction generator in charge of a slip power only. The boost converter is composed of a 3-leg IGBT and a boost inductor generating a direct current voltage of its source required for the H-bridge multi-level converter.

Abstract: A semiconductor package has a substrate having a first surface, a second surface, and a through hole opening. A heat spreader has a first surface, a second surface, and a plurality of notches formed on the second surface. A semiconductor die is coupled to the first surface of the heat spreader. The semiconductor die is electrically coupled to the substrate. An encapsulant is used to cover portions of the first surface of the substrate, portions of the first surface of the heat spreader, and the semiconductor die. A first set of solder balls is coupled to the second surface of the substrate. A second set of solder balls is coupled to the second surface of the heat spreader wherein the second set of solder balls is located in the notches.

Abstract: Disclosed herein is an electric power converting device and power converting method for controlling doubly-fed induction generators, which provides a synchronous generator for generating auxiliary electric power independently of a doubly-fed induction generator so as to generate electricity even in a system power-free environment, a grid-side converter is composed of a three-phase four-wire converter so as to generate a balanced voltage even in an unbalanced load condition and automatically synchronize a stator voltage of a doubly-fed induction generator and a system voltage with each other.

Abstract: A carrier frame and semiconductor package including a carrier frame provide improved thermal performance and mechanical stability for semiconductor packages using thin substrate materials. A metal carrier frame is attached to a substrate to provide support during and after the manufacturing process. A semiconductor die is mounted through an aperture in the center of the carrier frame and electrically connected to the substrate via wire bonding. The assembly is then encapsulated and singulated and a portion of the carrier frame remains in the package, improving thermal transfer from the semiconductor die. The assembly may further include a header for covering the aperture after the semiconductor die is wire bonded. The header/carrier combination may include means for improving encapsulant flow to the region under the header and surrounding the semiconductor die, which may include cut portions in the carrier frame or aligned holes through the carrier frame and header.

Abstract: A semiconductor package has a substrate of an approximate planar plate comprising of an insulative layer having a plurality of land holes formed in the vicinity of an inner circumference thereof and a plurality of electrically conductive patterns formed at a surface of the insulative layer, the electrically conductive patterns comprising a plurality of bond fingers formed in the vicinity of a central portion of the insulative layer and a plurality of lands for covering the land holes connected to the bond fingers. A semiconductor die is located at a central portion of the substrate. The semiconductor die has a plurality of bond pads formed at one surface thereof. A plurality of conductive bumps is used for coupling the bond pads of the semiconductor die to the bond fingers among the electrically conductive patterns of the substrate.

Abstract: A carrier frame and semiconductor package including a carrier frame provide improved thermal performance and mechanical stability for semiconductor packages using thin substrate materials. A metal carrier frame is attached to a substrate to provide support during and after the manufacturing process. A semiconductor die is mounted through an aperture in the center of the carrier frame and electrically connected to the substrate via wire bonding. The assembly is then encapsulated and singulated and a portion of the carrier frame remains in the package, improving thermal transfer from the semiconductor die. The assembly may further include a header for covering the aperture after the semiconductor die is wire bonded. The header/carrier combination may include means for improving encapsulant flow to the region under the header and surrounding the semiconductor die, which may include cut portions in the carrier frame or aligned holes through the carrier frame and header.

Abstract: A semiconductor package having a substrate including a die attach aperture and method for packaging a semiconductor die reduce or eliminate failures due to the “popcorn” effect caused by heating of water vapor during the manufacturing process. An aperture is provided in a substrate to permit die attach material to protrude to the outside of the semiconductor package, providing a path for the exit of water vapor from the die attach material during the manufacturing process. The popcorn effect is thereby eliminated, resulting in higher yields from the manufacturing process.