Abstract: A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.

Abstract: A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.

Abstract: The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29).

Abstract: The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.

Abstract: The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29).

Abstract: The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.

Abstract: A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.

Abstract: A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.

Abstract: The present invention provides a method for fabricating a MOS transistor (100) with suppression of edge transistor effect. In one embodiment of an NMOS, an elongate implant limb (110, HOa, 114) extends from each of two sidewalls (14a, 14b) of a p-type well (14) to partially wrap around each respective longitudinal end of the gate (20) and to overlay a portion thereof. In another embodiment, the elongate implant limb (110, 110a) extends into the drain/source drift region (32, 42). The NMOS transistor (100) thus fabricated allows the NMOS transistor to operate at relatively high voltages with reduced drain leakage current but with no additional masks or process time in the process integration.