Abstract: In a described embodiment, a sensor-based communication apparatus (100) is disclosed. The communication apparatus (100) comprises a plurality of sensor nodes (112) associated with respective unique pulse signatures (200) and adapted to communicate with respective sensors (113) with each sensor (113) configured to generate a sensory signal (113a) in response to a respective stimulus (113b). Each sensor node (112) is triggered, upon receipt of the corresponding sensory signal (113a), to transmit the associated unique pulse signature (200) independently and asynchronously through a transmission medium (110) shared by the sensor nodes (112), and the unique pulse signatures (200) transmitted by the sensor nodes (112) being a representation (300) of a stimulus event associated with the stimuli detected by the corresponding sensors (113). A method and a communication medium are also disclosed.

Abstract: In a described embodiment, a sensor-based communication apparatus (100) is disclosed. The communication apparatus (100) comprises a plurality of sensor nodes (112) associated with respective unique pulse signatures (200) and adapted to communicate with respective sensors (113) with each sensor (113) configured to generate a sensory signal (113a) in response to a respective stimulus (113b). Each sensor node (112) is triggered, upon receipt of the corresponding sensory signal (113a), to transmit the associated unique pulse signature (200) independently and asynchronously through a transmission medium (110) shared by the sensor nodes (112), and the unique pulse signatures (200) transmitted by the sensor nodes (112) being a representation (300) of a stimulus event associated with the stimuli detected by the corresponding sensors (113). A method and a communication medium are also disclosed.

Abstract: A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.

Abstract: A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.

Abstract: Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

Abstract: Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

Abstract: A circuit includes an antenna terminal for generating a current through electromagnetic induction. The circuit also includes a rectifier for receiving the current and generating a rectified power supply voltage. In addition, the circuit includes a voltage clamp for sinking at least some of the current from the antenna terminal based on the rectified power supply voltage from the rectifier. The voltage clamp could include a control circuit (such as an N-channel transistor and a resistor) for controlling the sinking of at least some of the current from the antenna terminal. The voltage clamp could also include a sink circuit (such as an N-channel transistor) for sinking at least some of the current from the antenna terminal. The voltage clamp could further include a sink control circuit (such as a P-channel transistor and a resistor) for activating and deactivating the sink circuit based on operation of the control circuit.

Abstract: An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circuit path with an antenna diode and at least one diode protection circuit coupled in series. The diode protection circuit reduces or prevents EOS current from flowing through the diode circuit path during an EOS event.

Abstract: An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circuit path with an antenna diode and at least one diode protection circuit coupled in series. The diode protection circuit reduces or prevents EOS current from flowing through the diode circuit path during an EOS event.

Abstract: A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver and an input of the output generator. In addition, the slew rate control circuit includes a voltage clamp for clamping a voltage on the electrical interconnection between two known voltage reference levels. The voltage clamp may include a first current source for providing driving capacity to a driver circuit to prevent the voltage on the electrical interconnection from falling below one known voltage reference level. The voltage clamp may also include a second current source and a third current source for providing sinking capacity to the driver circuit to prevent the voltage on the electrical interconnection from rising above the other known voltage reference level.

Abstract: A circuit includes an antenna terminal for generating a current through electromagnetic induction. The circuit also includes a rectifier for receiving the current and generating a rectified power supply voltage. In addition, the circuit includes a voltage clamp for sinking at least some of the current from the antenna terminal based on the rectified power supply voltage from the rectifier. The voltage clamp could include a control circuit (such as an N-channel transistor and a resistor) for controlling the sinking of at least some of the current from the antenna terminal. The voltage clamp could also include a sink circuit (such as an N-channel transistor) for sinking at least some of the current from the antenna terminal. The voltage clamp could further include a sink control circuit (such as a P-channel transistor and a resistor) for activating and deactivating the sink circuit based on operation of the control circuit.

Abstract: A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver and an input of the output generator. In addition, the slew rate control circuit includes a voltage clamp for clamping a voltage on the electrical interconnection between two known voltage reference levels. The voltage clamp may include a first current source for providing driving capacity to a driver circuit to prevent the voltage on the electrical interconnection from falling below one known voltage reference level. The voltage clamp may also include a second current source and a third current source for providing sinking capacity to the driver circuit to prevent the voltage on the electrical interconnection from rising above the other known voltage reference level.