Patents by Inventor Kian-Boon How

Kian-Boon How has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for extraction of electrical specifications from prelayout simulations
    Patent number: 10198545
    Abstract: Systems and methods for extracting one or more electrical specifications from a prelayout simulation of an integrated circuit design, where the one or more electrical specification are utilized to generate a physical layout of one or more components of an integrated circuit.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 5, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Tat Hin Tan, Kian Boon How, Chieu Fung Tan, My Chien Yee
  • Stress reduction on vias and yield improvement in layout design through auto generation of via fill
    Patent number: 8276104
    Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 25, 2012
    Assignee: Spansion LLC
    Inventors: Gregory Sylvester Emmanuel, Hui-Peng Ong, Kian-Boon How, Joseph Lin
  • STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THROUGH AUTO GENERATION OF VIA FILL
    Publication number: 20120151430
    Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Inventors: Gregory Sylvester EMMANUEL, Hui-Peng ONG, Kian-Boon HOW, Joseph LIN