Patents by Inventor Kian-Fui Seng

Kian-Fui Seng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9804983
    Abstract: A controlling method, a connector, and a memory storage device are provided. The controlling method includes following steps. A connection between the memory storage device and a host system is established. A first command is received from the host system and stored into a command queue. The command queue includes at least one second command after the first command is stored into the command queue. Whether a command number of the second commands is greater than a threshold is determined. The threshold is greater than 1. If the command number is greater than the threshold, a using right of the connection is obtained and a second command is executed by the memory storage device. If the command number is not greater than the threshold, a command from the host system is waited for. The using right of the connection belongs to the host system. Thereby, the system efficiency is improved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 31, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Kian-Fui Seng
  • Patent number: 9424206
    Abstract: A command executing method, a connector and a memory storage device are provided. The command executing method includes: receiving at least one command and at least one tag corresponding to the command from a host system, and temporarily storing the command in a command queue; transmitting the tag to the host system and executing the command; determining whether an operating status of the memory storage device meets a predetermined condition; and if the operating status meets the predetermined condition, transmitting a configuration message to the host system to release the tag from corresponding to the command. Accordingly, the access bandwidth of the memory storage device is increased.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: August 23, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Kian-Fui Seng
  • Patent number: 9058296
    Abstract: A data processing method, a memory storage device, and a memory control circuit unit are provided. Here, each physical address corresponds to one flag. The data processing method includes: receiving a reading command; reading first data stored in the physical addresses of a physical programming unit; determining whether a first flag in the physical programming unit is in a first status or a second status; transmitting decrypted first data or decrypted specific-format data to a host system according to whether the first flag is in the first status or the second status. Accordingly, the encryption operation may be simplified.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: June 16, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kian-Fui Seng, Ming-Hui Tseng
  • Patent number: 9037782
    Abstract: A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: May 19, 2015
    Assignee: Phison Electronics Corp.
    Inventors: Kian-Fui Seng, Ming-Hui Tseng, Ching-Hsien Wang
  • Publication number: 20150095663
    Abstract: A data processing method, a memory storage device, and a memory control circuit unit are provided. Here, each physical address corresponds to one flag. The data processing method includes: receiving a reading command; reading first data stored in the physical addresses of a physical programming unit; determining whether a first flag in the physical programming unit is in a first status or a second status; transmitting decrypted first data or decrypted specific-format data to a host system according to whether the first flag is in the first status or the second status. Accordingly, the encryption operation may be simplified.
    Type: Application
    Filed: November 28, 2013
    Publication date: April 2, 2015
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kian-Fui Seng, Ming-Hui Tseng
  • Publication number: 20150012670
    Abstract: A command executing method, a connector and a memory storage device are provided. The command executing method includes: receiving at least one command and at least one tag corresponding to the command from a host system, and temporarily storing the command in a command queue; transmitting the tag to the host system and executing the command; determining whether an operating status of the memory storage device meets a predetermined condition; and if the operating status meets the predetermined condition, transmitting a configuration message to the host system to release the tag from corresponding to the command. Accordingly, the access bandwidth of the memory storage device is increased.
    Type: Application
    Filed: August 21, 2013
    Publication date: January 8, 2015
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Kian-Fui Seng
  • Publication number: 20140223076
    Abstract: A controlling method, a connector, and a memory storage device are provided. The controlling method includes following steps. A connection between the memory storage device and a host system is established. A first command is received from the host system and stored into a command queue. The command queue includes at least one second command after the first command is stored into the command queue. Whether a command number of the second commands is greater than a threshold is determined. The threshold is greater than 1. If the command number is greater than the threshold, a using right of the connection is obtained and a second command is executed by the memory storage device. If the command number is not greater than the threshold, a command from the host system is waited for. The using right of the connection belongs to the host system. Thereby, the system efficiency is improved.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 7, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Kian-Fui Seng
  • Publication number: 20130246732
    Abstract: A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells.
    Type: Application
    Filed: June 21, 2012
    Publication date: September 19, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kian-Fui Seng, Ming-Hui Tseng, Ching-Hsien Wang
  • Patent number: 8086787
    Abstract: A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: December 27, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Ruei-Cian Chen, Chih-Kang Yeh, Kian-Fui Seng
  • Publication number: 20100057979
    Abstract: A data transmission method suitable for transmitting data from a cache to a plurality of flash memory groups through a single data bus in a flash memory storage system is provided. The data transmission method includes sequentially sorting and grouping data to be written at continuous logical addresses in the cache in unit of logical blocks. The data transmission method further includes respectively transmitting the grouped sector data into the flash memory groups through the data bus in an interleaving manner, wherein data in the same logical block is transmitted and written into physical blocks of the same flash memory group. Thereby, the data is prevented from being written into different physical blocks, and accordingly the lifespan of the flash memory storage system is prolonged.
    Type: Application
    Filed: December 3, 2008
    Publication date: March 4, 2010
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh, Ruei-Cian Chen, Kian-Fui Seng
  • Publication number: 20100023675
    Abstract: A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system.
    Type: Application
    Filed: November 6, 2008
    Publication date: January 28, 2010
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: RUEI-CIAN CHEN, Chih-Kang Yeh, Kian-Fui Seng