Patents by Inventor Kian Sin Sim

Kian Sin Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741515
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20190287937
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 10373924
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20180247908
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: May 1, 2018
    Publication date: August 30, 2018
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9966351
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9698114
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: July 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Publication number: 20160365325
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9449936
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20150179600
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20110169167
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Patent number: 7915060
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Publication number: 20100148365
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Patent number: 7692301
    Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Kum Foo Leong, Chee Key Chung, Kian Sin Sim
  • Patent number: 7670951
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Patent number: 7229913
    Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Kum Foo Leong, Chee Key Chung, Kian Sin Sim
  • Patent number: 6946737
    Abstract: The invention provides a via with improved resistance to failures due to delamination voids. In one embodiment, the via may extend from above to below a bottom conductor and include an anchor section. The anchor section may mechanically interlock the via with the bottom conductor to prevent the via from being detached from the bottom conductor.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: September 20, 2005
    Assignee: Intel Corporation
    Inventors: Jiun Hann Sir, Kian Sin Sim