Patents by Inventor Kian Sin Sim
Kian Sin Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741515Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: June 5, 2019Date of Patent: August 11, 2020Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20190287937Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: June 5, 2019Publication date: September 19, 2019Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
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Patent number: 10373924Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: May 1, 2018Date of Patent: August 6, 2019Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20180247908Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: May 1, 2018Publication date: August 30, 2018Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
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Patent number: 9966351Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: August 24, 2016Date of Patent: May 8, 2018Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Patent number: 9698114Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: March 25, 2011Date of Patent: July 4, 2017Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Publication number: 20160365325Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Patent number: 9449936Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: March 6, 2015Date of Patent: September 20, 2016Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20150179600Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: March 6, 2015Publication date: June 25, 2015Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20110169167Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: March 25, 2011Publication date: July 14, 2011Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Patent number: 7915060Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: February 26, 2010Date of Patent: March 29, 2011Assignee: Intel CorporationInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Publication number: 20100148365Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: February 26, 2010Publication date: June 17, 2010Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Patent number: 7692301Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.Type: GrantFiled: May 21, 2007Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Kum Foo Leong, Chee Key Chung, Kian Sin Sim
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Patent number: 7670951Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: June 27, 2005Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Patent number: 7229913Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.Type: GrantFiled: September 25, 2003Date of Patent: June 12, 2007Assignee: Intel CorporationInventors: Kum Foo Leong, Chee Key Chung, Kian Sin Sim
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Patent number: 6946737Abstract: The invention provides a via with improved resistance to failures due to delamination voids. In one embodiment, the via may extend from above to below a bottom conductor and include an anchor section. The anchor section may mechanically interlock the via with the bottom conductor to prevent the via from being detached from the bottom conductor.Type: GrantFiled: August 11, 2004Date of Patent: September 20, 2005Assignee: Intel CorporationInventors: Jiun Hann Sir, Kian Sin Sim