Abstract: The disclosure provides a movement determination method, a movement determination device, and a computer-readable storage medium. The method includes the following. In response to determining that a user has presented an initial movement corresponding to a to-be-detected movement, an anchor joint point among multiple joint points of the user is decided based on the to-be-detected movement. A movable range of each of the anchor joint points is decided. In response to determining that each of the anchor joint points leaves the corresponding movable range, it is determined that the user has stopped performing the to-be-detected movement.

Abstract: The disclosure provides a movement determination method, a movement determination device, and a computer-readable storage medium. The method includes the following. In response to determining that a user has presented an initial movement corresponding to a to-be-detected movement, an anchor joint point among multiple joint points of the user is decided based on the to-be-detected movement. A movable range of each of the anchor joint points is decided. In response to determining that each of the anchor joint points leaves the corresponding movable range, it is determined that the user has stopped performing the to-be-detected movement.

Abstract: The invention provides a human body detection method, a human body detection device, and a computer readable storage medium. The method includes the following. A plurality of image frames related to a human body is obtained. A plurality of joint coordinates are detected in each image frame, and a plurality of specific image frames are accordingly found out. An image region height corresponding to the human body in each specific image frame is obtained. A first joint coordinate of a first joint in each specific image frame is obtained. A second joint coordinate of a second joint in each specific image frame is obtained. An actual length between the first joint and the second joint is estimated based on a height of the human body and the image region height, the first joint coordinate, and the second joint coordinate in each specific image frame.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We perform a poly/Si interface amorphization implant to amorphize at least the poly/Si interface in the S/D areas and to from an amorphous region. We anneal the substrate to crystallize the amorphous region and the polysilicon layer over the amorphous region to form an elevated silicon region in the source/drain area. Next, source/drain regions in are formed in the elevated silicon regions and the substrate.