Abstract: A network interface controller includes a plurality of scatter gather circuits (104a-104d) connectable to a host via a bus (101). A packet buffer (112) is configured for communication with the scatter gather circuits (104a-104d). A plurality of access circuits (110a-110d) are configured to access external network connections. An optional forwarding engine (108) is selectable to generate routing information corresponding to data received via the access circuits (110a-110d) and to provide the routing information to the packet buffer (112).

Abstract: A network interface controller includes a plurality of scatter gather circuits (104a-104d) connectable to a host via a bus (101). A packet buffer (112) is configured for communication with the scatter gather circuits (104a-104d). A plurality of access circuits (110a-110d) are configured to access external network connections. An optional forwarding engine (108) is selectable to generate routing information corresponding to data received via the access circuits (110a-110d) and to provide the routing information to the packet buffer (112).

Abstract: A network interface controller includes a plurality of scatter gather circuits (104a-104d) connectable to a host via a bus (101). A packet buffer (112) is configured for communication with the scatter gather circuits (104a-104d). A plurality of access circuits (110a-110d) are configured to access external network connections. An optional forwarding engine (108) is selectable to generate routing information corresponding to data received via the access circuits (110a-110d) and to provide the routing information to the packet buffer (112).

Abstract: A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage locations associated with the host available to hold the data to be transferred to the host is provided from the host to the adaptor. An indication of the provided indication is maintained, for that transfer, by the host. Based on the indication of locations provided from the host to the adaptor, data is transferred to the at least one group of storage locations from the adaptor. An indication is provided from the adaptor to the host that the data transferring step has been completed with respect to the at least one group of storage locations. The host determines the locations corresponding to the at least one group of storage locations based on the indications maintained by the host and retrieving the data from the at least one group of storage locations based on the determination.

Abstract: A network interface controller includes a plurality of scatter gather circuits (104a-104d) connectable to a host via a bus (101). A packet buffer (112) is configured for communication with the scatter gather circuits (104a-104d). A plurality of access circuits (110a-110d) are configured to access external network connections. An optional forwarding engine (108) is selectable to generate routing information corresponding to data received via the access circuits (110a-110d) and to provide the routing information to the packet buffer (112).

Abstract: A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage locations associated with the host available to hold the data to be transferred to the host is provided from the host to the adaptor. An indication of the provided indication is maintained, for that transfer, by the host. Based on the indication of locations provided from the host to the adaptor, data is transferred to the at least one group of storage locations from the adaptor. An indication is provided from the adaptor to the host that the data transferring step has been completed with respect to the at least one group of storage locations. The host determines the locations corresponding to the at least one group of storage locations based on the indications maintained by the host and retrieving the data from the at least one group of storage locations based on the determination.

Abstract: A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit.

Abstract: An input/output flow control system for a processor system having an input/output request source (e.g., a processor) and a plurality of input/output request targets (e.g., I/O busses) uses a NACKing (negatively acknowledging) scheme to prevent a common I/O path from becoming blocked due to the blockage of one or more I/O buses. The system includes a flow controller associated with each of the targets for receiving input/output requests from the source, for accepting (ACKing) a request if the intended target can accept the request, and for NACKing a request if the intended target cannot accept the request. The system also includes a processor or source interface for resending the NACKed requests to the intended target and for cooperating with the flow controller so that the NACKed requests are accepted by the flow controller in the proper order.

Abstract: A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification desired. As addresses and access-type signals appear on the bus, the comparator simultaneously compares the bus information to access event register information to determine if the bus access meets access event register criteria. When matches occur, the comparator emits an appropriate signal to an event masking component. The local processor also loads the event masking component to selectively mask off unwanted event notifications as well as those performed by itself.

Abstract: A CMOS output buffer circuit for providing an output signal at an output terminal with a significant reduction in ground bounce includes a pull-up driver circuit (12), a pull-down driver circuit (14), and a control circuit (16). The pull-up driver circuit includes first and second resistive means for delaying the turn-on times of pull-up transistors. The pull-down driver circuit includes third and fourth resistive elements for delaying the turn-on times of pull-down transistors. Each of the first through fourth resistive elements (D1-D4) is formed of a transmission gate and serves to control the gate-to-source voltages applied to the respective gates of the pull-up and pull-down transistors.

Abstract: A CMOS output buffer circuit for providing an output signal at an output terminal which has a significant reduction in ground bounce over processing and power supply variations includes an output driver stage (12), a pull-up pre-driver circuit (14), a pull-down pre-diver circuit (16), and feedback means. The output driver stage is formed of a pull-up transistor (P1) and a pull-down transistor (N1). The feedback means is responsive to the output signal for controlling the rate of rise of the voltage at the gate electrode of the pull-down transistor so as to slow down its turn-on time when the output terminal is making a high-to-low transition, thereby significantly reducing the ground bounce. The feedback means is preferably formed of a capacitor (C2) having a first plate connected to the output terminal and a second plate coupled to the gate electrode of the pull-down transistor.

Abstract: An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source (114). The first current source is coupled to the base of the emitter follower transistor for generating a compensating current. The second current source is coupled to the emitters of the first and second input transistors for generating a gate current.

Abstract: A TTL-to-CML translator circuit includes a TTL input stage (20), a translation chain (22), a first CML differential pair (24), a level shifter (26), and a second CML differential pair (28). The first CML differential pair (24) is coupled between a TTL ground potential (GTTL) and a negative supply potential (VEE). The second CML differential pair (28) is connected between a CML ground potential (GCML) and the negative supply potential. The level shifter (26) serves to electrically isolate the TTL ground potential and the CML ground potential, thereby producing relatively noise free CML-compatible output signals.

Abstract: An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals includes an active pull-down circuit (120), a high level voltage clamping circuit (122), and ground bounce protection circuit (124) so as to provide a higher speed of operation with minimal power dissipation and a significant reduction in ground bounce noise. The ground bounce protection circuit is formed of a voltage-independent current source, a reference resistor (R15), and a switching transistor (Q15).

Abstract: A TTL buffer circuit includes an active turn-off means so as to provide faster output transitions without using excess power dissipation. The active turn-off means is formed of a Schottky diode (D402), a resistor (R417), and a Schottky bipolar transistor (Q414) which causes rapid switching of a pull-down transistor (Q413), thereby increasing the speed of the output transitions.