Patents by Inventor Ki-Bum Lee
Ki-Bum Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240167711Abstract: The simulation system for predicting heating and cooling loads of a building comprises the collection unit collecting measurement data of a target building from a BEMS, the identification unit identifying indoor and outdoor temperature, humidity, and insolation measured in the building in real time based on RTS method, the correlation derivation unit deriving a correlation between energy usage based on the BEMS measurement data collected by the collection unit and the cooling and heating loads according to indoor and outdoor temperature, humidity, and insolation identified by the identification unit, the simulation unit predicting a change in cooling and heating loads according to a change in at least one of pieces of measurement data based on the correlation derived from the correlation derivation unit to perform a simulation, and the information provision unit providing a simulation result from the simulation unit in a visible form to a user terminal.Type: ApplicationFiled: September 19, 2023Publication date: May 23, 2024Inventors: Tae Dong LEE, Won Jang PARK, Min Ho CHOI, Soo Hyun YANG, Moo Kyung SEO, Han Sung CHOI, Hye Mi LIM, Ji Hun PARK, So Jeong PARK, Ki Bum HAN, Hyeong Jae JEON
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Patent number: 11953066Abstract: The present disclosure relates to a brake disc including a braking part having a circular plate shape having a hollow portion and a plurality of coupling portions protruding and extending from an inner diameter surface thereof, and a hat part disposed in the hollow portion and having a plurality of insertion portions protruding laterally, in which the plurality of coupling portions is respectively coupled to the plurality of insertion portions, and the coupling portion of the braking part and the insertion portion of the hat part are joined to only one of an outboard portion or an inboard portion of the braking part. According to the present disclosure, it is possible to reduce noise occurring at a position at which the hat part and the braking part are coupled to each other and improve cooling performance.Type: GrantFiled: April 1, 2022Date of Patent: April 9, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, SEOHAN INDUSTRY CO., LTD.Inventors: Yoon-Cheol Kim, Kyung-Rok Choi, Sang-Bum Koh, Seong-Kweon Joo, Ki-Jeong Kim, Jae-Seok Lee
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Patent number: 11946541Abstract: A method of controlling an EOP of a powertrain may include determining, by a controller electrically connected to the EOP, whether an oil sloshing phenomenon in which it is difficult for oil to return to a space where an oil intake port of the EOP is positioned may occur while a vehicle is running; and reducing, by the controller, the revolutions per minute (RPM) of the EOP by a predetermined reduced RPM when it is determined that the oil sloshing phenomenon may occur.Type: GrantFiled: August 20, 2021Date of Patent: April 2, 2024Assignees: Hyundai Motor Company, Kia CorporationInventors: Sung Sik Choi, Kyung Moo Lee, Seong Min Son, Ki Bum Kim, Se Hwan Jo, Bong Uk Bae
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Patent number: 11916171Abstract: A display device includes a substrate, a first electrode and a second electrode which are spaced apart from each other in a second direction, light-emitting elements spaced apart from each other in the first direction, a first contact electrode electrically contacting the light-emitting elements, and a second contact electrode electrically contacting the light-emitting elements. The first contact electrode electrically contacts the first electrode through a first contact portion disposed on the first electrode, the second contact electrode electrically contacts the second electrode through a second contact portion disposed on the second electrode, the first contact portion is disposed on an end portion in the first direction of the first contact electrode, and the second contact portion is disposed on an end portion in the first direction of the second contact electrode.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun Wook Lee, Ki Bum Kim, Jin Taek Kim, Jung Eun Hong
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Patent number: 11917881Abstract: A display device includes light transmitting areas including a first light transmitting area and light emitting areas around the light transmitting areas and including a first light emitting area disposed around the first light transmitting area, wherein the first light emitting area includes a first-first light emitting area adjacent to a first portion of each of the light transmitting areas, a first-second light emitting area adjacent to a second portion of each of the light transmitting areas, a first-third light emitting area adjacent to a third portion of each of the light transmitting areas, and a first-fourth light emitting area disposed adjacent to a fourth portion of each of the light transmitting areas. The first-first to first-fourth light emitting areas each include at least one of first to third light emitting portions to emit light of first to third colors, respectively.Type: GrantFiled: September 14, 2022Date of Patent: February 27, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Woong Hee Jeong, Ki Bum Kim, Jin Yeong Kim, Hyang A Park, Tae Hoon Yang, Jong Chan Lee
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Patent number: 11670537Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.Type: GrantFiled: February 4, 2021Date of Patent: June 6, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
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Publication number: 20220370687Abstract: A three dimensional scaffold for generating cell or protein assemblies. This degradable scaffold can be applied to various types of cells. Also disclosed are methods of treating a condition by implanting the protein or cell assembly prepared according to the method described herein.Type: ApplicationFiled: May 24, 2022Publication date: November 24, 2022Applicant: Rutgers, The State University of New JerseyInventors: Ki-Bum Lee, Letao Yang
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Publication number: 20220283510Abstract: A dynamic interference lithography (DIL) device is provided. The device includes a laser source configured for providing a laser beam, a substrate stage configured for mounting a substrate, an at least partially convex curved mirror, and a spatial filter configured to divide the laser beam into a first beam portion directed towards the at least partially convex curved mirror and a second beam portion directed towards the substrate. The first beam portion is reflected by the at least partially convex curved mirror towards the substrate to form an interference pattern on the substrate.Type: ApplicationFiled: March 3, 2022Publication date: September 8, 2022Applicant: Rutgers, The State University of New JerseyInventors: Ki-Bum Lee, Letao Yang
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Publication number: 20220136972Abstract: A surface-enhanced Raman scattering (SERS) sensing system or platform and methods of using the same, where the platform comprises a graphene coated-homogeneous plasmonic metal hybrid array, which synergizes both electromagnetic mechanism (EM)- and chemical mechanism (CM)-based signal enhancement for achieving sensitive and reproducible detection of Raman signals. The system and methods of using such system or platform may be applied to the analyses of various bio/chemical molecules, such as but not limited to those found in cells, in a highly sensitive and selective manner.Type: ApplicationFiled: October 27, 2021Publication date: May 5, 2022Inventors: Ki-Bum LEE, Letao YANG
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Patent number: 11306326Abstract: This application discloses the compositions comprising biologically active synthetic nanoparticle constructs and methods of use thereof to modify gene expression including transcriptional activation and transcriptional repression.Type: GrantFiled: June 11, 2019Date of Patent: April 19, 2022Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEYInventors: Ki-Bum Lee, Sahishnu Patel
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Publication number: 20220049238Abstract: Disclosed are spheroidal hybrid biodegradable materials containing low dimensional manganese dioxide (MnO2) support structures and cells, methods of manufacture thereof, and methods of use thereof.Type: ApplicationFiled: August 17, 2021Publication date: February 17, 2022Applicant: Rutgers, The State University of New JerseyInventors: Ki-Bum Lee, Christopher Rathman, Letao Yang
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Patent number: 11215932Abstract: A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.Type: GrantFiled: June 5, 2020Date of Patent: January 4, 2022Assignees: SK hynix Inc., UIF (University Industry Foundation), Yonsei UniversityInventors: Sung Jae Kim, Song Yi Jeon, Chang Ouk Kim, Ki Bum Lee
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Publication number: 20210369653Abstract: Provided in the present specification is an ETV2 transcription factor comprising: a polyamide comprising a domain binding to DNA (DNA binding domain) of an ETV2 gene; a nuclear localization signal peptide; and a nano-particle.Type: ApplicationFiled: November 2, 2018Publication date: December 2, 2021Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Young Sup YOON, Ki Bum LEE, Hyeon Yeol CHO, Sy-Tsong CHUENG
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Publication number: 20210215679Abstract: Nanorod devices for isolating and characterizing target cellular components are provided. Methods of isolating, detecting, and/or characterizing the components are also provided. Methods of use and treatment are further disclosed, such as treating diseases identified using the nanorods and/or using differentiated stem cells identified using the provided nanorods.Type: ApplicationFiled: January 6, 2021Publication date: July 15, 2021Inventors: Ki-Bum Lee, Jin-Ho Lee, Jeong-Woo Choi, Jin-Ha Choi
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Publication number: 20210183689Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.Type: ApplicationFiled: February 4, 2021Publication date: June 17, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
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Publication number: 20210139772Abstract: Disclosed herein are embodiments of a composition comprising at least three layers. Layers one and two each either comprises a sensitizer or an emitter, typically a metal ion or a dye, and the third layer may or may not comprise a sensitizer or emitter. Upon exposure to light, such as infrared light, the composition produces visible and/or UV light. The composition may further comprise a capping moiety, a therapeutic agent, an uptake enhancer, a detection moiety that binds to a desired target, a quenching moiety, or a combination thereof. The composition may be a particle, such as a nanoparticle, or it may be a planar composition. Also disclosed are embodiments of a method for using the composition, including, but not limited to, a method for delivering a therapeutic agent, or a method for detecting a target, such as a biological target.Type: ApplicationFiled: December 30, 2020Publication date: May 13, 2021Applicant: Rutgers, the State University of New JerseyInventors: Ki-Bum Lee, Hudifah Rabie, Nicholas Pasquale, Yixiao Zhang
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Publication number: 20210063895Abstract: A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.Type: ApplicationFiled: June 5, 2020Publication date: March 4, 2021Inventors: Sung Jae KIM, Song Yi JEON, Chang Ouk KIM, Ki Bum LEE
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Patent number: 10930544Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.Type: GrantFiled: August 14, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
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Patent number: D1021689Type: GrantFiled: August 9, 2022Date of Patent: April 9, 2024Assignee: NEUBILITYInventors: Sang Min Lee, Hyun Gon Kim, Ki Joon Seong, Jin Bum Kim
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Patent number: D1026732Type: GrantFiled: August 9, 2022Date of Patent: May 14, 2024Assignee: NEUBILITYInventors: Sang Min Lee, Hyun Gon Kim, Ki Joon Seong, Jin Bum Kim