Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

Abstract: A non-volatile memory cell is provided. The non-volatile memory cell includes a first conductivity type semiconductor substrate, second conductivity type source/drain regions longitudinally arranged in a direction to be parallel to each other and separated from each other by a predetermined distance in the semiconductor substrate, such that the second conductive source/drain regions define a channel region therebetween. A tunnel oxide layer is formed on the semiconductor substrate. First conductive layer patterns are formed on the tunnel oxide layer on the channel formation region in the form of islands. Buried oxide layers fill spaces between the adjacent first conductive layer patterns. Second conductive layer patterns are formed on the upper surfaces and the upper side surfaces of the first conductive layer patterns and arranged so that their edges are extended to some surfaces of the buried oxide layers.

Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

Abstract: A non-volatile memory cell is provided. The non-volatile memory cell includes a first conductivity type semiconductor substrate, second conductivity type source/drain regions longitudinally arranged in a direction to be parallel to each other and separated from each other by a predetermined distance in the semiconductor substrate, such that the second conductive source/drain regions define a channel region therebetween. A tunnel oxide layer is formed on the semiconductor substrate. First conductive layer patterns are formed on the tunnel oxide layer on the channel formation region in the form of islands. Buried oxide layers fill spaces between the adjacent first conductive layer patterns. Second conductive layer patterns are formed on the upper surfaces and the upper side surfaces of the first conductive layer patterns and arranged so that their edges are extended to some surfaces of the buried oxide layers.

Abstract: A method for fabricating a mask read only memory (ROM) is provided. A plurality of word lines functioning as a gate electrode of a cell transistor and a plurality of first anti-reflective layer patterns are sequentially formed on a semiconductor substrate. An insulator layer is formed over the entire surface of the semiconductor substrate where the plurality of first anti-reflective layer patterns and the plurality of word lines are formed. A spacer is formed at the side walls of the respective word lines by anisotropically etching the insulator layer until the plurality of word lines are exposed. A second anti-reflective layer is formed over the entire surface of the semiconductor substrate where the spacer is formed. A photoresist pattern opening the upper portion of a predetermined region of at least one word line selected among the plurality of word lines of the cell transistor to be programmed is formed on the second anti-reflective layer.