Abstract: The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN 0_0 to REGN 3_5 for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.

Abstract: An output control unit controls a drive terminal for a BEMF detection object phase to a high-impedance state in a mask term. A BEMF detection unit detects a voltage of the drive terminal for the detection object phase when a center tap voltage is set as a reference as BEMF in a PWM on-term for remaining two phases per PWM period in the mask term and asserts a zero-crossing signal when the voltage is reduced to zero. A PWM fixing unit fixes the remaining two phases to the PWM on-terms in a first term from a predetermined timing after an amplitude level of BEMF becomes smaller than a BEMF threshold amplitude to assertion of the zero-crossing signal. The BEMF detection unit continuously detects BEMF in the first term.

Abstract: The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN 0_0 to REGN 3_5 for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.

Abstract: An output control unit controls a drive terminal for a BEMF detection object phase to a high-impedance state in a mask term. A BEMF detection unit detects a voltage of the drive terminal for the detection object phase when a center tap voltage is set as a reference as BEMF in a PWM on-term for remaining two phases per PWM period in the mask term and asserts a zero-crossing signal when the voltage is reduced to zero. A PWM fixing unit fixes the remaining two phases to the PWM on-terms in a first term from a predetermined timing after an amplitude level of BEMF becomes smaller than a BEMF threshold amplitude to assertion of the zero-crossing signal. The BEMF detection unit continuously detects BEMF in the first term.

Abstract: A motor driving device and a motor system that can reduce a torque ripple of a motor are provided. The current control loop detects a drive current of the motor, detects an error between the detected value of the drive current and a current indication value as a target value of the drive current, and determines the duty of the PWM signal reflecting the error concerned. The back EMF phase detector detects the phase of a back electromotive force of each phase in the motor. The torque correction unit calculates a first torque correction coefficient of a periodic function based on the phase variations in the three phases of the back electromotive force, and corrects the current indication value superimposing the first torque correction coefficient on the current indication value.

Abstract: The phase of a drive current of a motor is optimized. The phase arithmetic unit PHCAL calculates a drive voltage phase ?drv to converge the phase difference between the reference voltage phase ?bemf and the reference current phase ?i to zero based on a prescribed arithmetic expression. The phase correction unit PHCP determines the phase ?drvR after the correction by adding a correction value to the phase ?drv, and the magnitude of the correction value is updated by a feedback control so as to converge to a prescribed value the phase difference between the reference voltage phase ?bemf and the reference current phase ?i which are inputted. A PWM controller shifts an energization control timing synchronized with the reference voltage phase ?bemf based on the corrected phase ?drvR, and generates the PWM signal for controlling the drive voltage to a sine wave shape.

Abstract: A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.

Abstract: A motor driving device and a motor system that can reduce a torque ripple of a motor are provided. The current control loop detects a drive current of the motor, detects an error between the detected value of the drive current and a current indication value as a target value of the drive current, and determines the duty of the PWM signal reflecting the error concerned. The back EMF phase detector detects the phase of a back electromotive force of each phase in the motor. The torque correction unit calculates a first torque correction coefficient of a periodic function based on the phase variations in the three phases of the back electromotive force, and corrects the current indication value superimposing the first torque correction coefficient on the current indication value.

Abstract: A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.

Abstract: There are provided a motor drive device and a motor system that can reduce the torque ripple of a motor. An SPM drive unit includes a plurality of high side transistors and low side transistors coupled to drive terminals of multiple phases respectively, and applies drive voltages to the drive terminals, using a PWM signal. A back electromotive force voltage phase detection unit detects each of back electromotive force voltage phases of the multiple phases. A drive voltage phase generation unit determines one of drive voltage phases in each of the multiple phases at the time of applying the drive voltages so that each of drive current phases of the multiple phases has a phase variation opposite in direction and equal to each of relative phase variations of the back electromotive force voltage phases of the multiple phases.

Abstract: The phase of a drive current of a motor is optimized. The phase arithmetic unit PHCAL calculates a drive voltage phase ?drv to converge the phase difference between the reference voltage phase ?bemf and the reference current phase ?i to zero based on a prescribed arithmetic expression. The phase correction unit PHCP determines the phase ?drvR after the correction by adding a correction value to the phase ?drv, and the magnitude of the correction value is updated by a feedback control so as to converge to a prescribed value the phase difference between the reference voltage phase ?bemf and the reference current phase ?i which are inputted. A PWM controller shifts an energization control timing synchronized with the reference voltage phase ?bemf based on the corrected phase ?drvR, and generates the PWM signal for controlling the drive voltage to a sine wave shape.

Abstract: The present invention is intended to reduce noise and vibration of a motor. A first duty correction circuit generates a first corrected duty instruction value which changes with an increment same as an increment of a duty instruction value and in which an offset value as a constant is reflected. A second duty correction circuit generates a second corrected duty instruction value which changes with an increment different from an increment of the duty instruction value. A selector outputs, as the corrected duty instruction value, either one of the first corrected duty instruction value and the second corrected duty instruction value in accordance with a magnitude relation between the duty instruction value and a duty reference value.

Abstract: The present invention realizes a calibration operation for detecting a motor speed, without employing digital correcting by an external CPU. The calibration operation calculates a comparison reference value corresponding to aback EMF detection signal of a back EMF detector circuit when a zero current flows through a motor and when an arm is fixed. Accordingly, the back EMF detection signal of the back EMF detector circuit is set as the first value and the second value responding to the non-zero current flowing through the motor, and the semiconductor integrated circuit calculates the comparison reference value from the first value and the second value. The difference between the comparison reference value and the comparison input value as the back EMF detection signal of the back EMF detector circuit is reduced by adjusting the gain of an internal amplifier of the back EMF detector circuit by an adjustment unit.

Abstract: The present invention is intended to reduce noise and vibration of a motor. A first duty correction circuit generates a first corrected duty instruction value which changes with an increment same as an increment of a duty instruction value and in which an offset value as a constant is reflected. A second duty correction circuit generates a second corrected duty instruction value which changes with an increment different from an increment of the duty instruction value. A selector outputs, as the corrected duty instruction value, either one of the first corrected duty instruction value and the second corrected duty instruction value in accordance with a magnitude relation between the duty instruction value and a duty reference value.

Abstract: The present invention realizes a calibration operation for detecting a motor speed, without employing digital correcting by an external CPU. The calibration operation calculates a comparison reference value corresponding to aback EMF detection signal of a back EMF detector circuit when a zero current flows through a motor and when an arm is fixed. Accordingly, the back EMF detection signal of the back EMF detector circuit is set as the first value and the second value responding to the non-zero current flowing through the motor, and the semiconductor integrated circuit calculates the comparison reference value from the first value and the second value. The difference between the comparison reference value and the comparison input value as the back EMF detection signal of the back EMF detector circuit is reduced by adjusting the gain of an internal amplifier of the back EMF detector circuit by an adjustment unit.

Abstract: The disclosed invention achieves a significant reduction in the noise and vibration of a brushless motor from a startup up to the number of steady revolutions. To drive the brushless motor from stop up to the number of steady revolutions, when the arithmetic sequencer detects a rise of a clock signal CARYCLK, current control arithmetic is executed. On detecting a fall of the clock signal, the arithmetic sequence determines whether a division control signal DIVCNT has changed. If this signal has changed, soft switch arithmetic is executed. When the division control signal has not changed or after the completion of soft switching arithmetic, the arithmetic sequencer determines whether a rise of a mask signal MASK has occurred during one cycle of the PWM carrier signal CARYCLK. If a rise of the mask signal has not occurred, the operation returns to the first step. If a rise of the mask signal has occurred, PLL control arithmetic is executed, then the operation returns to the first step.

Abstract: The disclosed invention achieves a significant reduction in the noise and vibration of a brushless motor from a startup up to the number of steady revolutions. To drive the brushless motor from stop up to the number of steady revolutions, when the arithmetic sequencer detects a rise of a clock signal CARYCLK, current control arithmetic is executed. On detecting a fall of the clock signal, the arithmetic sequence determines whether a division control signal DIVCNT has changed. If this signal has changed, soft switch arithmetic is executed. When the division control signal has not changed or after the completion of soft switching arithmetic, the arithmetic sequencer determines whether a rise of a mask signal MASK has occurred during one cycle of the PWM carrier signal CARYCLK. If a rise of the mask signal has not occurred, the operation returns to the first step. If a rise of the mask signal has occurred, PLL control arithmetic is executed, then the operation returns to the first step.

Abstract: A drive control device of a DC brushless multi-phase motor performs the speed control of the motor in place microprocessor, the burden on the microprocessor is relieved. The drive control device detects a zero crossing point of the back electromotive force in the non-energizing phase to perform the energizing switching to the coils by the PLL control, and includes a current detection circuit that detects currents flowing through the coils to perform the speed control of the motor based on the detected currents. The drive control device also, compares outputs from speed error detection circuit with outputs from the current detection circuit to determine the currents to be made to flow through the coils, and thereby controls the current output circuit.

Abstract: Currents of sine waveforms can be fed through coils by a relatively small-sized circuit, and thereby, highly dense magnetic storage can be realized with less rotation variations and a driving control circuit of a motor rotating at a low noise level can be provided. A coil of one phase of a three-phase brushless motor is driven with full amplitude at which an applied voltage becomes equal to a source voltage, and a coil of one of other phases is driven with gradually changing voltages so that a current of sine waveform is delivered, and a coil of the remaining phase is driven by feedback control so that a total current flowing through all coils becomes a predetermined current value.

Abstract: A drive control device of a DC brushless multi-phase motor performs the speed control of the motor in place microprocessor, the burden on the microprocessor is relieved. The drive control device detects a zero crossing point of the back electromotive force in the non-energizing phase to perform the energizing switching to the coils by the PLL control, and includes a current detection circuit that detects currents flowing through the coils to perform the speed control of the motor based on the detected currents. The drive control device also, compares outputs from speed error detection circuit with outputs from the current detection circuit to determine the currents to be made to flow through the coils, and thereby controls the current output circuit.