Abstract: A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The source/drain regions, formed in the pillar/trench sidewalls, couple the column cells serially into bitlines. The rows of the array are each coupled by a wordline. A second set of trenches separates the columns of cells.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of the emitters and has a thickness substantially equal to a height of the emitters above the substrate. The porous dielectric layer may be formed by oxidation of porous polycrystalline silicon. The display also includes an extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters. The display further includes a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters. The porous dielectric layer results in columns having less capacitance compared to prior art displays.

Abstract: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.

Abstract: A dielectric layer containing an atomic layer deposited hafnium tantalum film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. In an embodiment, a hafnium tantalum oxide film is formed by depositing hafnium and tantalum by atomic layer deposition onto a substrate surface. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited hafnium tantalum oxide film, and methods for forming such structures.

Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

Abstract: An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

Abstract: Atomic layer deposited dielectric layers containing a lanthanum hafnium oxide layer and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. In an embodiment, a lanthanum hafnium oxide layer is formed by depositing hafnium and lanthanum by atomic layer deposition onto a substrate surface. Embodiments include methods and apparatus in which precursors to deposit the lanthanum include a trisethylcyclopentadionatolanthanum precursor, a tris (2,2,6,6-tetramethl-3,5-heptanediaonato)lanthanum (III)precursor, a trisdipyvaloylmethanatolanthanum precursor, or a tris (2,2,6,6-tetramethyl-3,5-heptanedionato)lanthanum (III) tetraglyme adduct precursor.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of praseodymium oxide (PrXOY) and zirconium oxide (ZrOZ) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. The nanolaminate layered dielectric structure is formed by depositing praseodymium by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing zirconium onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. A nanolaminate layered dielectric layer of praseodymium oxide and zirconium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.

Abstract: A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide can be thermally stable, crystalline hafnium oxide and the lanthanum oxide can be thermally stable, crystalline lanthanum oxide. A transistor may comprise the composite dielectric as a gate dielectric. A capacitor may comprise the composite dielectric as a capacitor dielectric.

Abstract: A metal oxynitride layer formed by atomic layer deposition of a plurality of reacted monolayers, the monolayers comprising at least one each of a metal, an oxide and a nitride. The metal oxynitride layer is formed from zirconium oxynitride, hafnium oxynitride, tantalum oxynitride, or mixtures thereof. The metal oxynitride layer is used in gate dielectrics as a replacement material for silicon dioxide. A semiconductor device structure having a gate dielectric formed from a metal oxynitride layer is also disclosed.

Abstract: A dielectric layer containing an atomic layer deposited insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include conducting a number of annealing processes between a number of atomic layer deposition cycles for forming the metal oxide film. In an embodiment, a titanium aluminum oxide film is formed by depositing titanium and/or aluminum by atomic layer deposition onto a substrate surface. The deposited titanium and/or aluminum is annealed using atomic oxygen. After annealing, a layer of titanium aluminum oxide is formed on the annealed layer to form a contiguous layer of titanium aluminum oxide. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited titanium aluminum oxide film, and methods for forming such structures.

Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

Abstract: Atomic layer deposited lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. In an embodiment, a lanthanum aluminum oxide dielectric layer is formed by depositing aluminum and lanthanum by atomic layer deposition onto a substrate surface in which precursors to deposit the lanthanum include a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor.

Abstract: A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure for use in a variety of electronic devices. The lanthanide oxide dielectric layer is formed by depositing lanthanum by atomic layer deposition onto a substrate surface using a trisethylcyclopentadionatolanthanum precursor or a trisdipyvaloylmethanatolanthanum precursor. A ruthenium or a conductive ruthenium oxide gate may be formed on the lanthanide oxide dielectric layer. A ruthenium gate on a lanthanide oxide dielectric layer provides a gate structure that effectively prevents a reaction between the gate and the lanthanide oxide dielectric layer.

Abstract: A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure for use in a variety of electronic devices. The lanthanide oxide dielectric layer is formed by depositing lanthanum by atomic layer deposition onto a substrate surface using a trisethylcyclropentadienatolanthanum precursor or a trisdipyvaloylmethanatolanthanum precursor. A ruthenium or a conductive ruthenium oxide gate may be formed on the lanthanide oxide dielectric layer. A ruthenium gate on a lanthanide oxide dielectric layer provides a gate structure that effectively prevents a reaction between the gate and the lanthanide oxide dielectric layer.

Abstract: The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips.

Abstract: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.