Abstract: A high-density semiconductor device includes a first input/output line connected among a plurality of banks on a core area storing data, so that it transmits data, a second input/output line connected to a data pad capable of performing data input/output operations at a Peri-area, so that it transmits data, a first repeater connected between the first input/output line and the second input/output line, for transmitting data of the first input/output line to the second input/output line in response to a read enable signal enabled by a read command, and a second repeater connected between the first input/output line and the second input/output line, for transmitting data of the second input/output line to the first input/output line in response to a write enable signal enabled by a write command.

Abstract: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line.

Abstract: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line.

Abstract: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line.

Abstract: A high-density semiconductor device includes a first input/output line connected among a plurality of banks on a core area storing data, so that it transmits data, a second input/output line connected to a data pad capable of performing data input/output operations at a Peri-area, so that it transmits data, a first repeater connected between the first input/output line and the second input/output line, for transmitting data of the first input/output line to the second input/output line in response to a read enable signal enabled by a read command, and a second repeater connected between the first input/output line and the second input/output line, for transmitting data of the second input/output line to the first input/output line in response to a write enable signal enabled by a write command.

Abstract: An internal signal test device tests a cycle of a specific internal signal by distinguishing a high level period and a low level period of the internal signal, at a wafer and package state by using an external test equipment. The internal signal test device comprises a refresh cycle generating unit, an input/output selecting control unit and an output buffer. The refresh cycle generating unit generates a refresh cycle signal having a predetermined cycle at entry of a refresh mode. The input/output selecting control unit selectively outputs the refresh cycle signal and a data signal in response to a test mode signal. The output control unit outputs an output signal from the input/output selecting control unit to an external output pin in response to an output clock signal controlled by the test mode signal.

Abstract: A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration.

Abstract: A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration.

Abstract: A data output driver of a combination type of a synchronous dynamic random access memory (SDRAM) device operated in both of a single data rate (SDR) mode and a double data rate (DDR) mode, the data output driver includes a first input/output line connected between a drain of a pull-up transistor and a data input/output pad, a second input/output line connected between a drain of a pull-down transistor and the data input/output pad, at least one switching unit formed on each of the first input/output line and the second input/output line, and at least one resistor parallel-connected with the switch and formed on each of the first input/output line and the second input/output line, wherein the switching unit is turned on or turned off by selecting one of a SDR mode and a DDR mode.

Abstract: A data input device in a semiconductor device, includes a data strobe signal input buffer, which driven in response to a selection signal of a data input/output mode, for receiving a data strobe signal; a data input buffer driven in response to the selection signal; a repeater, which receives the selection signal and the data strobe signal input, outputs a first control signal of a first logic level when the selection signal is activated, and a second control signal of a second logic level when the selection signal is inactivated; and a latch for latching data provided from the data input buffer in response to the first control signal outputted from the repeater, wherein the latch is disabled when the second control signal is provided from the repeater.

Abstract: A data output driver of a combination type of a synchronous dynamic random access memory (SDRAM) device operated in both of a single data rate (SDR) mode and a double data rate (DDR) mode, the data output driver includes a first input/output line connected between a drain of a pull-up transistor and a data input/output pad, a second input/output line connected between a drain of a pull-down transistor and the data input/output pad, at least one switching unit formed on each of the first input/output line and the second input/output line, and at least one resistor parallel-connected with the switch and formed on each of the first input/output line and the second input/output line, wherein the switching unit is turned on or turned off by selecting one of a SDR mode and a DDR mode.

Abstract: A data input device in a semiconductor device, includes a data strobe signal input buffer, which driven in response to a selection signal of a data input/output mode, for receiving a data strobe signal; a data input buffer driven in response to the selection signal; a repeater, which receives the selection signal and the data strobe signal input, outputs a first control signal of a first logic level when the selection signal is activated, and a second control signal of a second logic level when the selection signal is inactivated; and a latch for latching data provided from the data input buffer in response to the first control signal outputted from the repeater, wherein the latch is disabled when the second control signal is provided from the repeater.

Abstract: Disclosed are a semiconductor memory device with a mode register that prevents the semiconductor device from undesirably entering into a deep power down mode during the beginning of a power up and a method for controlling a deep power down mode therein. An internal power supply voltage generator generates an internal power supply voltage of the semiconductor memory device. A clock buffer buffers external clock and clock enable signals to generate internal clock and clock enable signals. A command decoder generates an intermediate deep power down mode entry signal or a mode register setting signal. A mode register setting latch circuit latches the mode register setting signal from the command decoder. A deep power down mode controller generates a final deep power down mode entry signal. A semiconductor memory device is accordingly prevented from undesirably entering into a deep power down mode during beginning of a power up.

Abstract: Disclosed are a semiconductor memory device with a mode register that prevents the semiconductor device from undesirably entering into a deep power down mode during the beginning of a power up and a method for controlling a deep power down mode therein. An internal power supply voltage generator generates an internal power supply voltage of the semiconductor memory device. A clock buffer buffers external clock and clock enable signals to generate internal clock and clock enable signals. A command decoder generates an intermediate deep power down mode entry signal or a mode register setting signal. A mode register setting latch circuit latches the mode register setting signal from the command decoder. A deep power down mode controller generates a final deep power down mode entry signal. A semiconductor memory device is accordingly prevented from undesirably entering into a deep power down mode during beginning of a power up.