Abstract: A semiconductor memory apparatus may include a write data polarity change unit and a read data polarity change unit. The write data polarity change unit may invert a first data based on a write signal and a first bank address signal, and generate a write polarity change data. The read data polarity change unit may invert data outputted from a memory bank based on a read signal and the first bank address signal, and generate a read polarity change data.

Abstract: A semiconductor memory apparatus may include a write data polarity change unit and a read data polarity change unit. The write data polarity change unit may invert a first data based on a write signal and a first bank address signal, and generate a write polarity change data. The read data polarity change unit may invert data outputted from a memory bank based on a read signal and the first bank address signal, and generate a read polarity change data.

Abstract: A semiconductor memory apparatus may include a write data bus inversion unit and a write data polarity change unit. The write data bus inversion unit may invert a level of an input data and may generate an inversion change data when a majority of the input data have a predetermined level. The write data polarity change unit may invert a level of the inversion change data based on a write signal and a first bank address signal and generate a polarity change data.

Abstract: A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. The signal generation unit, in the first mode, outputs the first trigger signal in response to a first clock signal, and, in the second mode, retains the first trigger signal in a first state regardless of the first clock signal.

Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: A test circuit of a semiconductor apparatus may include a period signal counting block configured to count a period signal by a predetermined number of times, and enable an overflow signal. The test circuit of the semiconductor apparatus may include a clock signal counting block configured to count an internal clock signal until the overflow signal is enabled, and may output clock counting codes. The test circuit of the semiconductor apparatus may include an update register configured to receive and store the clock counting codes based on the overflow signal.

Abstract: A semiconductor memory apparatus may include a write data bus inversion unit and a write data polarity change unit. The write data bus inversion unit may invert a level of an input data and may generate an inversion change data when a majority of the input data have a predetermined level. The write data polarity change unit may invert a level of the inversion change data based on a write signal and a first bank address signal and generate a polarity change data.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: A semiconductor memory device includes a memory cell array including a normal region for storing a plurality of data, an error information region for storing a plurality of error information data corresponding to the plurality of normal data, respectively, and a redundancy region for replacing the normal region, an error detection unit suitable for detecting an error on the plurality of data in response to the plurality of error information data, and storing an error location information, which indicates a storage region of a data having an error in the normal and redundancy regions, based on an error detection result, and a repair operation unit suitable for replacing the storage region, which is indicated by the error location information, by the redundancy region during a repair operation period.

Abstract: A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. The signal generation unit, in the first mode, outputs the first trigger signal in response to a first clock signal, and, in the second mode, retains the first trigger signal in a first state regardless of the first clock signal.

Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal

Abstract: A semiconductor memory device includes a unit memory bank having a plurality of memory cell mats, which shares a local data line, and divided by a row address; and at least one dummy cell mat disposed between the plurality of memory cell mat.

Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal.

Abstract: A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.

Abstract: A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.

Abstract: A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.

Abstract: A test circuit of a semiconductor apparatus may include a period signal counting block configured to count a period signal by a predetermined number of times, and enable an overflow signal. The test circuit of the semiconductor apparatus may include a clock signal counting block configured to count an internal clock signal until the overflow signal is enabled, and may output clock counting codes. The test circuit of the semiconductor apparatus may include an update register configured to receive and store the clock counting codes based on the overflow signal.

Abstract: A semiconductor apparatus includes a back bias control block, a first back bias switching block and second back bias switching block. The back bias control block is configured to generate a first P channel control signal and a second N channel control signal. The first back bias switching block is configured to provide one of first and second high voltages as a first P channel back bias of a first circuit in response to the first P channel control signal, and to provide one of first and second low voltages as a first N channel back bias of the first circuit in response to the first N channel control signal. The second back bias switching block is configured to provide one of the first and second high voltages as a second P channel back bias of a second circuit in response to the second P channel control signal, and to provide one of the first and second low voltages as a second N channel back bias of the second circuit in response to the second N channel control signal.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.