Abstract: A multiple layer pixel architecture for an active matrix display is provided having a common bus line on a metal level separate from that on which the gate electrodes of the thin-film transistors (TFTs) are formed. A multilayer electronic structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.

Abstract: A multiple layer pixel architecture for an active matrix display is provided having a common bus line on a metal level separate from that on which the gate electrodes of the thin-film transistors (TFTs) are formed. A multilayer electronic structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.

Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.

Abstract: A multiple layer pixel architecture for an active matrix display is provided in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the thin-film transistors (TFTS) are formed. A multilayer electronic structure adapted to solution deposition, the structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separeted by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.

Abstract: A semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighboring device.

Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.

Abstract: A method of processing a flexible encapsulation scheme to encapsulate a flexible device, such as a display device in order to provide structural support for the display module. An upper transparent encapsulation layer covers and protects the media and active area of the device. A lower encapsulation layer is deposited over the under side of the display to complete the encapsulation and the two protective encapsulation layers are sealed. A driver housing may be positioned at the opposite end of the device to the overlap region of the encapsulation layers in order to protect the driver electronics.

Abstract: A semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighboring device. Such a configuration allows for improved device performance, resulting from features such as a greater storage capacitance.

Abstract: A method of processing a flexible encapsulation scheme to encapsulate a flexible device, such as a display device in order to provide structural support for the display module. An upper transparent encapsulation layer covers and protects the media and active area of the device. A lower encapsulation layer is deposited over the under side of the display to complete the encapsulation and the two protective encapsulation layers are sealed. A driver housing may be positioned at the opposite end of the device to the overlap region of the encapsulation layers in order to protect the driver electronics.

Abstract: The present invention relates to a multiple layer pixel architecture for an active matrix display in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the TFTs are formed. A multilayer electronic structure adapted to solution deposition, the structure including a thin film transistor (TFT) for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure comprises a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.

Abstract: A field effect transistor is provided which comprises a gate electrode, a source electrode, a drain electrode, at least one organic semiconducting layer, and a hole transport layer for transferring holes from said source and drain electrodes to said organic semiconducting layer, wherein said hole transport layer comprises a layered metal chalcogenide. Processes for depositing a thin layer of a layered metal dichalcogenide on a substrate and for producing top gate structures on a layered metal chalcogenide layer in the manufacture of field effect transistors according to the invention are also provided.