Abstract: Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

Abstract: A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

Abstract: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

Abstract: A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

Abstract: Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

Abstract: The claimed invention provides a method of a remotely accessing a decentralized device in a conventional fiber to the premises network via a centralized display device operatively connected to an optical line terminal. The invention further provides the decentralized device adapted to be remotely accessed by the display device. The invention further provides a debug managed entity instance.

Abstract: An optical network unit for managing digital subscriber line (xDSL) connections to a passive optical network. According to one embodiment, the optical network unit comprises data structures in the form of managed entities that are issued by the optical network unit for managing each of the xDSL connections. Each managed entity is associated with one or more network features and comprises one or more elements further comprising relationships to other managed entities, attributes, actions, and notifications. The passive optical network provides a data connection between the individual xDSL subscriber connections and external networks, such as the Internet and a switched telephone network.

Abstract: An optical network unit for managing digital subscriber line (×DSL) connections to a passive optical network. According to one embodiment, the optical network unit comprises data structures in the form of managed entities that are issued by the optical network unit for managing each of the ×DSL connections. Each managed entity is associated with one or more network features and comprises one or more elements further comprising relationships to other managed entities, attributes, actions, and notifications. The passive optical network provides a data connection between the individual ×DSL subscriber connections and external networks, such as the Internet and a switched telephone network.

Abstract: Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.

Abstract: An apparatus is provided for conducting solid phase oligomer synthesis. The apparatus includes a reaction vessel in which a solid phase support is contained. The reaction vessel has a top opening through which gases and solvents can be delivered by way of a series of conduits and valves. The reaction vessel is interconnected through a bottom opening therein and through a series of conduits and valves with a vessel or series of vessels containing a reagent or series of reagents, respectively, required for the synthetic reaction. The reagent vessel serves a both a source of reagent delivered to the reaction vessel and as a repository for unused reagent returned thereto from the reaction vessel. Reagent delivery and mixing is gas-driven using an associated source of an inert gas.