Abstract: A volatile memory device comprises a memory cell array including a plurality of memory cells storing data, and control logic controlling read and write operations for the plurality of memory cells. The control logic is configured to receive a command instructing a self-refresh operation from an external host device, to perform the self-refresh operation in response to the received command, to request the external host device to transfer data stored in the plurality of memory cells in response to a performance time of the self-refresh operation having elapsed a first threshold time, to monitor a read command received from the external host device in response to receiving a notification of self-refresh operation termination and a read command from the external host device, and to enter a power off state in response to the read command not being received for a second threshold time.

Abstract: A memory device includes at least one bank including memory cells, and a register corresponding to the at least one bank. The bank includes a plurality of rows that are arranged in a row direction, and a plurality of count cells, each of which stores count data associated with the number of times of access of each of the plurality of rows. The register stores an address and count data, which are associated with at least one row among the plurality of rows.

Abstract: A memory device includes a bank that includes a plurality of rows, each row including memory cells and a set of count cells configured to store count data associated with the number of times each of the plurality of rows is accessed, and a row hammer management circuit configured to manage the count data of each row of the plurality of rows of the bank, and reset the count data corresponding to each row of the plurality of rows, in response a normal refresh operation being performed.

Abstract: A memory device includes a bank including memory cells. The bank includes rows arranged in a row direction, count cells, each storing row hammer count data associated with a number of times a corresponding row of the rows is accessed, and extended count cells, each storing information about one or more of extended row hammer count data associated with the number of times the corresponding row of the row is accessed or a number of times a row hammer refresh operation is executed on the corresponding row of rows.

Abstract: A memory device includes a bank comprising a plurality of memory cells connected to a plurality of wordlines and a plurality of column selection lines, a row hammer management circuit performing a read-modify-write (RMW) operation on count memory cells to read count data corresponding to an activated wordline among the plurality of wordlines, wherein the plurality of memory cells include the count memory cells configured to store the count data representing a number of access to the activated wordline, updating the read count data, and writing the updated count data in the count memory cells, and a control logic selecting a first count column selection line connected to the count memory cells from among the plurality of column selection lines based on writing characteristics of each of the plurality of column selection lines.

Abstract: An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

Abstract: A memory module includes: a circuit board including a plurality of signal lines to which a command is applied; and a first memory device mounted on a first surface of the circuit board, connected to the plurality of signal lines, including a first mode register, and configured to: operate in a standard mode or a mirrored mode, based on a value set in the first mode register, set a value corresponding to the mirrored mode in the first mode register, based on a first command applied to the plurality of signal lines, wherein at least one bit of a plurality of command/address bits in the first command is swapped with at least one bit of a plurality of command/address bits in a second command.

Abstract: A memory device includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

Abstract: A memory device includes at least one bank including a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may store normal data and may be connected to a plurality of first wordlines, the second sub-bank may store metadata corresponding to the normal data and may be connected to a plurality of second wordlines, and metadata for normal data corresponding to each of the first wordlines may be stored in each of second wordlines, respectively corresponding to the first wordlines.

Abstract: A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may include a normal data region connected to a plurality of first wordlines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second wordlines and storing metadata corresponding to the normal data, the plurality of first wordlines may match the plurality of second wordlines to form a plurality of wordline pairs, and the first sub-bank and the second sub-bank may share a row hammer region storing a number of access times to the plurality of wordline pairs.

Abstract: A memory device includes a bank connected to a plurality of wordlines, a first global input and output (GIO) line, and a second GIO line formed to have a larger length than the first GIO line in a column direction. One of the first GIO line and the second GIO line may be allocated for metadata.

Abstract: An example memory device includes a memory cell array, a row hammer management circuit, and a read-modify-write (RMW) driver. The memory cell array includes a plurality of memory cell rows and stores count data for a number of accesses to each memory cell row. The row hammer management circuit performs an RMW operation that reads out count data corresponding to a target memory cell row among the memory cell rows, updates the read-out count data, and writes the updated count data in the memory cell array. The RMW driver generates control signals to control the RMW operation based on a precharge command. The target memory cell row is precharged after a predetermined time is elapsed from a time point where the precharge command is applied.

Abstract: A memory device includes a bank connected to a plurality of wordlines and a plurality of column select lines (CSLs). Among the plurality of wordlines, every r-th wordline in a column direction may be allocated for metadata where r is a positive integer.

Abstract: A method of operating a memory configured to communicate with a memory controller, the method includes: temporarily storing a unique identification (ID) for each of a plurality of memory devices included in the memory to each of the plurality of memory devices; selecting a target memory device from among the plurality of memory devices; and permanently or substantially permanently programming, in the target memory device, a unique ID corresponding to the target memory device.

Abstract: A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

Abstract: A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.

Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.