Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: A picture generation apparatus and a control method thereof are disclosed. An embodiment of the present disclosure provides a picture generation apparatus including a light source; a Spatial Light Modulator (SLM) configured to output an image using light transmitted from the light source; and a control unit configured to control the light source and the SLM based on at least one of illuminance of the surroundings or content of the image.

Abstract: Disclosed herein is a novel polymer having a structure based on a biodegradable polymer. In the novel polymer, the biodegradable polymer has at least one kind of functional groups from among a hydroxyl group and a carboxyl group, wherein the biodegradable polymer bears a functional group conjugated with a nitric oxide-releasing compound and a different functional group substituted with a photopolymerizable functional group, the nitric oxide-releasing compound comprising a NO donor. Also provided is a nanofiber fabricated from the modified biodegradable polymer. The nanofiber can be fabricated by electrospinning the novel polymer.

Abstract: A battery pack and a method of controlling the same. The battery pack includes: a first battery module that includes at least one battery cell; a second battery module that includes at least one battery cell electrically connected to the first battery module; a charge/discharge control unit that breaks or connects a charge/discharge path of each of the first battery module and the second battery module; a first battery management unit that controls the first battery module; and a second battery management unit that generates a signal for controlling switches included in the charge/discharge control unit by referring to a state of the second battery module, wherein the first battery management unit and the second battery management unit are connected in parallel to the charge/discharge control unit.

Abstract: A battery pack and a method of controlling the same. The battery pack includes: a first battery module that includes at least one battery cell; a second battery module that includes at least one battery cell electrically connected to the first battery module; a charge/discharge control unit that breaks or connects a charge/discharge path of each of the first battery module and the second battery module; a first battery management unit that controls the first battery module; and a second battery management unit that generates a signal for controlling switches included in the charge/discharge control unit by referring to a state of the second battery module, wherein the first battery management unit and the second battery management unit are connected in parallel to the charge/discharge control unit.

Abstract: A driver circuit for a plasma display panel is disclosed. The driver circuit has a switch which is shared between the reset driver portion of the driver circuit and the sustain driver portion of the driver circuit. The driver circuit sharing the switch between the two portions is smaller and cheaper than other driver circuits.

Abstract: A method of driving a plasma display apparatus may include supplying a first voltage to the X electrodes during a first reset period of the reset period, supplying, using energy stored in the energy recovery circuit, a ramp waveform voltage that rises from the first voltage signal to a second voltage to the X electrodes during a second reset period of the reset period, biasing the X electrodes with the second voltage during at least a first sub-period of a third reset period of the reset period, supplying a ramp pulse waveform voltage that rises from a third voltage to a fourth voltage to the Y electrodes during a second portion of the first reset period, and supplying a ramp pulse waveform voltage that falls from the third voltage to a fifth voltage to the Y electrodes during the third reset period.

Abstract: A linearity coil of a horizontal deflecting circuit includes a core; a winding connected in series to a horizontal deflecting coil and wound on the core; and a pair of permanent magnets respectively fixed to both ends of the core in the direction of increasing a magnetic force line induced to the core.

Abstract: An improved surge protecting circuit which can protect the power source and the internal and external circuit elements of an electronic product by absorbing external surges through ground. The protecting circuit according to the present invention is connected between an AC input terminal and an AC ground pattern. The protecting circuit includes surge absorption patterns having an arc discharge gap of preferably 0.25 mm, which is less than a specified safety distance, which is typically 5 mm, so as to absorb the external surges transmitted through the terminal to the AC ground pattern and a varistor connected between the surge absorption patterns and the AC ground patterns.

Abstract: An electronic product with a standby power source includes a main power circuit for receiving a commercial AC through a power switch and generating a main power source by full-wave rectifying the AC through a diode bridge, and a standby power circuit for receiving the AC and generating the standby power source by full-wave rectifying the AC through another diode bridge, the standby power circuit and the main power circuit being formed on one printed circuit board, and the standby power circuit having an additional ground pattern isolated from a ground pattern of the main power circuit.

Abstract: A reproduction error correction circuit for a video reproduction system includes a line-storage memory for temporarily storing composite video signal samples, which memory is operated to provide both for time-base correction and for drop-out compensation. The memory is cyclically supplied sequential write addresses descriptive of pixel locations along a horizontal scan line, generated at a rate that tracks any jitter in the input video signal selectively used for writing over the previous contents of the memory. The memory is cyclically supplied sequential read addresses offset 1/2 scan line from the write addresses, generated at a stable rate equal to an average over several scan lines of the rate at which write addresses are generated. This provides for time-base error correction. When a drop-out is detected, overwriting of video signal samples already stored in the single line-storage memory is prohibited.

Abstract: A reproduction error correction circuit for a video reproduction system includes a line-storage memory for temporarily storing composite video signal samples, which memory is operated to provide both for time-base correction and for drop-out compensation. The memory is cyclically supplied sequential write addresses descriptive of pixel locations along a horizontal scan line, generated at a rate that tracks any jitter in the input video signal selectively used for writing over the previous contents of the memory. The memory is cyclically supplied sequential read addresses offset 1/2 scan line from the write addresses, generated at a stable rate equal to an average over several scan lines of the rate at which write addresses are generated. This provides for time-base error correction. When a drop-out is detected, overwriting of video signal samples already stored in the single line-storage memory is prohibited.

Abstract: A circuit for detecting the recording/playback mode of a system, e.g., a video tape recorder (VTR), for recording/playing back an image signal on/from a recording medium, using first and second input signals derived from pilot signals also recorded on the recording medium. The circuit includes a first peak value detector for detecting the peak value of the first input signal, and for generating a first output signal representative of the peak value of the first input signal, and a second peak value detector for detecting the peak value of the second input signal, and for generating a second output signal representative of the peak value of the second input signal.

Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

Abstract: A FM detection system using a phase locked loop (PPL 20) and including: a wave shaping comparator (7) for accepting a signal V.sub.CO2 from a voltage controlled oscillator (4) which is 90.degree. out of phase with a control signal V.sub.CO1 from the voltage controlled oscillator (4), the comparator reshaping the signal to a square wave; an in-lock detector (8) for accepting the square wave and a frequency modulated input signal (VFM) to provide a sum frequency and a difference frequency; a low-pass filter (9) cutting off the sum frequency component, and filtering out the difference frequency signal when the PLL (20) is unlocked; a comparator (10) for comparing the output of the low-pass filter (9) with a reference voltage (V.sub.