Abstract: In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.

Abstract: In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.

Abstract: In a method of calculating a shift value of a cell contact, a reference region and a correction region may be set on an image of an actual cell block. The cell block may include a plurality of actual cell contacts formed using a mask. Each of preliminary shift values of the actual cell contacts with respect to target cell contacts in a target cell block to be formed using the mask may be measured based on the image. The preliminary shift values of the actual cell contacts in the reference region may be minimized. Actual shift values of the actual cell contacts in the correction region with respect to the minimized preliminary shift values may be calculated. Thus, the mask may be corrected using the accurately measured shift values so that the cell contacts may have designed positions.

Abstract: In a method of calculating a shift value of a cell contact, a reference region and a correction region may be set on an image of an actual cell block. The cell block may include a plurality of actual cell contacts formed using a mask. Each of preliminary shift values of the actual cell contacts with respect to target cell contacts in a target cell block to be formed using the mask may be measured based on the image. The preliminary shift values of the actual cell contacts in the reference region may be minimized. Actual shift values of the actual cell contacts in the correction region with respect to the minimized preliminary shift values may be calculated. Thus, the mask may be corrected using the accurately measured shift values so that the cell contacts may have designed positions.

Abstract: In a method of calculating a shift value of a cell contact, a reference region and a correction region may be set on an image of an actual cell block. The cell block may include a plurality of actual cell contacts formed using a mask. Each of preliminary shift values of the actual cell contacts with respect to target cell contacts in a target cell block to be formed using the mask may be measured based on the image. The preliminary shift values of the actual cell contacts in the reference region may be minimized. Actual shift values of the actual cell contacts in the correction region with respect to the minimized preliminary shift values may be calculated. Thus, the mask may be corrected using the accurately measured shift values so that the cell contacts may have designed positions.

Abstract: In a method of calculating a shift value of a cell contact, a reference region and a correction region may be set on an image of an actual cell block. The cell block may include a plurality of actual cell contacts formed using a mask. Each of preliminary shift values of the actual cell contacts with respect to target cell contacts in a target cell block to be formed using the mask may be measured based on the image. The preliminary shift values of the actual cell contacts in the reference region may be minimized. Actual shift values of the actual cell contacts in the correction region with respect to the minimized preliminary shift values may be calculated. Thus, the mask may be corrected using the accurately measured shift values so that the cell contacts may have designed positions.

Abstract: The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines. Further, the pair of vertical transistors is electrically connected to the two adjacent buried bit lines. Electronic systems including the semiconductor device and related methods are also provided.

Abstract: The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines. Further, the pair of vertical transistors is electrically connected to the two adjacent buried bit lines. Electronic systems including the semiconductor device and related methods are also provided.

Abstract: Semiconductor devices are provided. The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors are disposed at both sides of one of the word lines, respectively. Further, the pair of vertical transistors are electrically connected to two adjacent ones of the buried bit lines, respectively. Electronic systems including the semiconductor device and related methods are also provided.

Abstract: The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines. Further, the pair of vertical transistors is electrically connected to the two adjacent buried bit lines. Electronic systems including the semiconductor device and related methods are also provided.

Abstract: A phase change memory device having a 3-D stack structure and a fabrication method for making the same are presented. The phase change memory device includes a semiconductor substrate, a word line structure and one or more phase change structures. The word line structure extends in one first direction on the semiconductor substrate. The one or more phase change structures extend mutually in parallel from one sidewall of the word line structure. The, the memory cell including a switching device, one side of the switching device contacted with the one sidewall of the word line structure, a heating electrode formed on the other side portion of the switching device, and a phase change pattern, one sidewall of the phase change pattern contacted with the heating electrode.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: A phase change memory device having a 3-D stack structure and a fabrication method for making the same are presented. The phase change memory device includes a semiconductor substrate, a word line structure and one or more phase change structures. The word line structure extends in one first direction on the semiconductor substrate. The one or more phase change structures extend mutually in parallel from one sidewall of the word line structure. The, the memory cell including a switching device, one side of the switching device contacted with the one sidewall of the word line structure, a heating electrode formed on the other side portion of the switching device, and a phase change pattern, one sidewall of the phase change pattern contacted with the heating electrode.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: The present invention relates to safe authentication. According to the present invention, a security access service method includes an authentication step by the input of text, an access location tracking step, an authentication step by the input of coordinates, and an access history report step.