Abstract: Provided herein is a mechanism to controllably move a wire within a flexible tubular member, the wire including opposed wire ends extending outwardly of a proximal end of the flexible tubular member, comprising a drive mechanism and a coupling located between the drive mechanism and the wire end, wherein movement of the coupling in the direction of the wire end results in opposed motion of the wire end.

Abstract: Disclosed are an apparatus and method of manufacturing an oxide film having a uniform composition and thickness. The apparatus includes a lower chamber including a reaction space, a susceptor to support a substrate, a chamber lid including gas injection ports, a gas distribution module between the chamber lid and the susceptor and connected to the gas injection ports, a first source container module comprising a first source gas having a first vapor pressure, a first carrier gas supply module supplying a first carrier gas to the first source container module, a second source container module comprising a second source gas having a second vapor pressure, a force gas supply module supplying a force gas, and a reactant gas supply module supplying a reactant gas.

Abstract: Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

Abstract: A duration of time for a first idle state of a memory sub-system is determined, where the memory sub-system includes an active state and a second idle state. A first command is received to transition from the active state to the second idle state. In response to the first command, the memory sub-system is transitioned to the first idle state. The memory sub-system is transitioned from the first idle state to the second idle state in response to an expiration of the duration of time.

Abstract: A duration of time for a first idle state of a memory sub-system is determined, where the memory sub-system includes an active state and a second idle state. A first command is received to transition from the active state to the second idle state. In response to the first command, the memory sub-system is transitioned to the first idle state. The memory sub-system is transitioned from the first idle state to the second idle state in response to an expiration of the duration of time.

Abstract: A transitory idle state is established for a memory sub-system that can be transitioned from an active state to one or more idle states including the transitory idle state and a deep idle state. A power consumption metric and transition time for each idle state is identified. A transitional energy metric is determined for each idle state based on the corresponding power consumption metric transition time. An energy target time is determined for the transitory idle state. Based on the energy target time, an idle state optimization time is determined for the transitory idle state. The memory sub-system is maintained in the transitory idle state for a duration of the idle state optimization time.

Abstract: A transitory idle state is established for a memory sub-system that can be transitioned from an active state to one or more idle states including the transitory idle state and a deep idle state. A power consumption metric and transition time for each idle state is identified. A transitional energy metric is determined for each idle state based on the corresponding power consumption metric transition time. An energy target time is determined for the transitory idle state. Based on the energy target time, an idle state optimization time is determined for the transitory idle state. The memory sub-system is maintained in the transitory idle state for a duration of the idle state optimization time.

Abstract: A method is described, which includes receiving, by firmware of a memory subsystem, a memory request that requests access to a set of memory components managed by a hardware controller of the memory subsystem and transmitting a sub-request in response to receipt of the memory request. The method further includes receiving, by the firmware from the hardware controller, status information describing the current operating state of the hardware controller at the time of receipt of the sub-request, wherein the status information is transmitted by the hardware controller in response to the sub-request and determining, by the firmware, whether the status information indicates that the hardware controller is operating under an exception condition.

Abstract: Methods and systems configured to increment one or more counters, including read command total, write command total, total blocks written and read, and low read or write queue depth, when a read or write command is received. When a request for a total device busy time is received, a total device busy time is determined and provided using one or more of the counters and one or more corresponding timing factors.

Abstract: Methods and systems configured to increment one or more counters, including read command total, write command total, total blocks written and read, and low read or write queue depth, when a read or write command is received. When a request for a total device busy time is received, a total device busy time is determined and provided using one or more of the counters and one or more corresponding timing factors.

Abstract: A solar cell can include a single crystalline semiconductor substrate; an emitter region positioned on an incident surface of the substrate, forming a p-n junction with the single crystalline semiconductor substrate; a first passivation layer positioned on a rear surface of the substrate and made of an oxide material; a back surface field layer positioned on the first passivation layer and forming a hetero junction with the single crystalline semiconductor substrate; a first electrode electrically connected to the emitter region; and a second electrode electrically connected to the single crystalline semiconductor substrate

Abstract: Disclosed are an apparatus and method of manufacturing an oxide film having a uniform composition and thickness. The apparatus includes a lower chamber including a reaction space, a susceptor to support a substrate, a chamber lid including gas injection ports, a gas distribution module between the chamber lid and the susceptor and connected to the gas injection ports, a first source container module comprising a first source gas having a first vapor pressure, a first carrier gas supply module supplying a first carrier gas to the first source container module, a second source container module comprising a second source gas having a second vapor pressure, a force gas supply module supplying a force gas, and a reactant gas supply module supplying a reactant gas.

Abstract: A normally-off, heterojunction field effect transistor includes an intrinsic cubic-phase gallium nitride (c-GaN) substrate and an aluminum gallium nitride (AlGaN) capping layer disposed on the intrinsic c-GaN substrate. The AlGaN capping layer includes a first sublayer of intrinsic c-phase AlxGa1-xN disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase AlxGa1-xN disposed on the first sublayer, and wherein the second sublayer is of a second thickness and is doped with a dopant. An insulating layer is disposed on the AlGaN capping layer, wherein the insulating layer is of a fourth thickness. A source electrode, a drain electrode, and a gate electrode are positioned adjacent to and on top of the insulating layer, respectively.

Abstract: A normally-off, heterojunction field effect transistor includes an intrinsic cubic-phase gallium nitride (c-GaN) substrate and an aluminum gallium nitride (AlGaN) capping layer disposed on the intrinsic c-GaN substrate. The AlGaN capping layer includes a first sublayer of intrinsic c-phase AlxGa1-xN disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase AlxGa1-xN disposed on the first sublayer, and wherein the second sublayer is of a second thickness and is doped with a dopant. An insulating layer is disposed on the AlGaN capping layer, wherein the insulating layer is of a fourth thickness. A source electrode, a drain electrode, and a gate electrode are positioned adjacent to and on top of the insulating layer, respectively.

Abstract: The present invention proposes a graphene lithium ion capacitor formed of a graphene material and including electrodes pre-doped with lithium ions. There is provided a graphene lithium ion capacitor according to an exemplary embodiment of the present invention, including: at least a part of a cathode and an anode formed of a graphene material; a lithium sacrificial electrode electrically connected to the anode so as to provide pre-doping lithium ions to the anode; a separator disposed between the cathode and the anode; and an electrolyte bonded to the cathode and the anode in a state of being dissociated into ions to flow current between the cathode and the anode, in which the anode is formed of a multilayered structure so as to adsorb lithium ions provided from the lithium sacrificial electrode on the surface and accommodate the lithium ions intercalated between graphene layers, and at least a part of the surface and the multilayered structure are formed of lithium carbide by reaction with the lithium ions.

Abstract: A solar cell includes a first conductivity type crystalline semiconductor substrate, a first amorphous silicon region, a first electrode, and a second electrode. The crystalline semiconductor substrate may include a plurality of pyramidal-shaped projections or a plurality of reverse-pyramidal shape depressions on at least one surface thereof. The first amorphous silicon region may be positioned on the crystalline semiconductor substrate and have a second conductivity type opposite the first conductivity type. The first electrode may be positioned on the first amorphous silicon region, and a second electrode positioned on the substrate. At least one pyramidal-shaped projection or at least one reverse-pyramidal shape depression may include two adjacent inclination surfaces, and a rounded edge portion where the two adjacent inclination surfaces meet.

Abstract: A solar cell includes a crystalline semiconductor substrate containing a first impurity of a first conductive type, a first non-crystalline impurity semiconductor region directly contacting with the crystalline semiconductor substrate to form a p-n junction with the crystalline semiconductor substrate and including a first portion in which a second impurity of a second conductive type is doped with a first impurity doping concentration and a second portion in which the second impurity is doped with a second impurity doping concentration, the first impurity doping concentration being less than an impurity doping concentration of the crystalline semiconductor substrate and the second impurity doping concentration being greater than the impurity doping concentration of the crystalline semiconductor substrate, a first electrode connected to the first non-crystalline impurity semiconductor region, and a second electrode connected to the crystalline semiconductor substrate.

Abstract: A solar cell is discussed. The solar cell includes a substrate made of a crystalline semiconductor, an emitter region made of a non-crystalline semiconductor forming a p-n junction with the substrate, a first passivation region positioned on the substrate and made of an oxide material, a first electrode electrically connected to the emitter region, and a second electrode electrically connected to the substrate.

Abstract: A method of installing a software program in a host device, which is required for the host device to communicate with a peripheral device. The method includes the steps of coupling the host device to the peripheral device, which contains the software program stored in a memory device contained in the peripheral device, utilizing a USB serial interface; uploading the software program from the peripheral device to the host device; and installing the software program in the host device thereby allowing communication between the host device and the peripheral device.