Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel. The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.

Abstract: A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

Abstract: A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

Abstract: An interface circuit includes a first amplifier circuit comprising a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, a first output node configured to output a first output signal, a second output node configured to output a second output signal, and a variable impedance circuit comprising a first impedance circuit connected to the first output node, and a second impedance circuit connected to the second output node. A code generator circuit is configured to generate a first control code and a second control code. The first impedance circuit is configured to adjust an impedance thereof based on the first control code, and the second impedance circuit is configured to adjust an impedance thereof based on the second control code.

Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.

Abstract: A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.

Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel. The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.

Abstract: A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

Abstract: A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

Abstract: A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

Abstract: A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

Abstract: A calibration device includes a first comparator that outputs a first result of comparing a level of a first voltage of a first node and a level of a reference voltage, a second comparator that outputs a second result of comparing the level of the first voltage and a level of a second voltage of a second node, and a control signal generator that outputs a first signal for adjusting a first resistance value of a first resistor circuit based on the first result and to output a second signal for adjusting a second resistance value of a second resistor circuit based on the second result. The first node is between the first resistor circuit and a reference resistor, and the second node is between the second resistor circuit and a third resistor circuit which is adjusted to have the same resistance value as the first resistance value.

Abstract: A calibration device includes a first comparator that outputs a first result of comparing a level of a first voltage of a first node and a level of a reference voltage, a second comparator that outputs a second result of comparing the level of the first voltage and a level of a second voltage of a second node, and a control signal generator that outputs a first signal for adjusting a first resistance value of a first resistor circuit based on the first result and to output a second signal for adjusting a second resistance value of a second resistor circuit based on the second result. The first node is between the first resistor circuit and a reference resistor, and the second node is between the second resistor circuit and a third resistor circuit which is adjusted to have the same resistance value as the first resistance value.