Patents by Inventor Kiichi Makuta

Kiichi Makuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10461053
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Publication number: 20190027455
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: SHINYA SUZUKI, Kiichi Makuta
  • Publication number: 20170243847
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Application
    Filed: May 5, 2017
    Publication date: August 24, 2017
    Inventors: SHINYA SUZUKI, KIICHI MAKUTA
  • Patent number: 9659926
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 23, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Patent number: 9558708
    Abstract: A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 31, 2017
    Assignee: Synaptics Japan GK
    Inventors: Yoshinori Ura, Kiichi Makuta, Toshikazu Arai, Jun Uchida, Keita Tsubakino
  • Patent number: 9514684
    Abstract: A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: December 6, 2016
    Assignee: Synpatics Display Devices GK
    Inventors: Keita Tsubakino, Kiichi Makuta, Toshikazu Arai, Yoshinori Ura
  • Publication number: 20160315078
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Inventors: SHINYA SUZUKI, Kiichi MAKUTA
  • Patent number: 9472526
    Abstract: A semiconductor device includes a main structure, active bumps and dummy bumps which are provided over a surface of the main structure. The active bumps are arranged in first to n-th rows. The active bumps positioned in each row are arrayed in a first direction with a predetermined first pitch. The first to n-th rows of the active bumps are arrayed in a second direction perpendicular to the first direction. For j being any integer from one to n?1, a (j+1)-th row are shifted in the second direction from a j-th row of the active bumps by a second pitch and shifted in the first direction from the j-th row of the active bumps by a predetermined sub-pitch. The dummy bumps are arrayed in the first direction with the first pitch, and the length of each of the dummy bumps in the second direction is longer than the second pitch.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: October 18, 2016
    Assignee: Synaptics Japan GK
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Patent number: 9391066
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 12, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Publication number: 20150279800
    Abstract: A semiconductor device includes a main structure, active bumps and dummy bumps which are provided over a surface of the main structure. The active bumps are arranged in first to n-th rows. The active bumps positioned in each row are arrayed in a first direction with a predetermined first pitch. The first to n-th rows of the active bummps are arrayed in a second direction perpendicular to the first direction. For j being any integer from one to n?1 a (j+1)-th row are shifted in the second direction from a j-th row of the active bumps by a second pitch and shifted in the first direction from the j-th row of the active bumps by a predetermined sub-pitch. The dummy bumps are arrayed in the first direction with the first pitch, and the length of each of the dummy bumps in the second direction is longer than the second pitch.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 1, 2015
    Inventors: Shinya SUZUKI, Kiichi MAKUTA
  • Publication number: 20150255452
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 10, 2015
    Inventors: Shinya SUZUKI, Kiichi MAKUTA
  • Patent number: 9082370
    Abstract: Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: July 14, 2015
    Assignee: SYNAPTICS DISPLAY DEVICES GK
    Inventors: Iori Shiraishi, Kiichi Makuta, Satoshi Saito, Masaru Iizuka
  • Publication number: 20150124006
    Abstract: A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 7, 2015
    Inventors: Yoshinori URA, Kiichi MAKUTA, Toshikazu ARAI, Jun UCHIDA, Keita TSUBAKINO
  • Publication number: 20150022562
    Abstract: A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: Keita Tsubakino, Kiichi Makuta, Toshikazu Arai, Yoshinori Ura
  • Publication number: 20140118300
    Abstract: Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 1, 2014
    Applicant: Renesas SP Drivers Inc.
    Inventors: Iori Shiraishi, Kiichi Makuta, Satoshi Saito, Masaru Iizuka
  • Publication number: 20140008793
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Application
    Filed: September 17, 2013
    Publication date: January 9, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Patent number: 8564127
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: October 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Publication number: 20110018129
    Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
    Type: Application
    Filed: June 3, 2010
    Publication date: January 27, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Shinya Suzuki, Kiichi Makuta
  • Patent number: 7376015
    Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: May 20, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
  • Publication number: 20050265114
    Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
    Type: Application
    Filed: August 5, 2005
    Publication date: December 1, 2005
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri