Patents by Inventor Kiichi Makuta
Kiichi Makuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10461053Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: GrantFiled: September 21, 2018Date of Patent: October 29, 2019Assignee: Renesas Electronics CorporationInventors: Shinya Suzuki, Kiichi Makuta
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Publication number: 20190027455Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: ApplicationFiled: September 21, 2018Publication date: January 24, 2019Inventors: SHINYA SUZUKI, Kiichi Makuta
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Publication number: 20170243847Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: ApplicationFiled: May 5, 2017Publication date: August 24, 2017Inventors: SHINYA SUZUKI, KIICHI MAKUTA
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Patent number: 9659926Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: GrantFiled: July 1, 2016Date of Patent: May 23, 2017Assignee: Renesas Electronics CorporationInventors: Shinya Suzuki, Kiichi Makuta
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Patent number: 9558708Abstract: A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.Type: GrantFiled: November 5, 2014Date of Patent: January 31, 2017Assignee: Synaptics Japan GKInventors: Yoshinori Ura, Kiichi Makuta, Toshikazu Arai, Jun Uchida, Keita Tsubakino
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Patent number: 9514684Abstract: A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.Type: GrantFiled: July 15, 2014Date of Patent: December 6, 2016Assignee: Synpatics Display Devices GKInventors: Keita Tsubakino, Kiichi Makuta, Toshikazu Arai, Yoshinori Ura
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Publication number: 20160315078Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: ApplicationFiled: July 1, 2016Publication date: October 27, 2016Inventors: SHINYA SUZUKI, Kiichi MAKUTA
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Patent number: 9472526Abstract: A semiconductor device includes a main structure, active bumps and dummy bumps which are provided over a surface of the main structure. The active bumps are arranged in first to n-th rows. The active bumps positioned in each row are arrayed in a first direction with a predetermined first pitch. The first to n-th rows of the active bumps are arrayed in a second direction perpendicular to the first direction. For j being any integer from one to n?1, a (j+1)-th row are shifted in the second direction from a j-th row of the active bumps by a second pitch and shifted in the first direction from the j-th row of the active bumps by a predetermined sub-pitch. The dummy bumps are arrayed in the first direction with the first pitch, and the length of each of the dummy bumps in the second direction is longer than the second pitch.Type: GrantFiled: March 30, 2015Date of Patent: October 18, 2016Assignee: Synaptics Japan GKInventors: Shinya Suzuki, Kiichi Makuta
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Patent number: 9391066Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: GrantFiled: May 14, 2015Date of Patent: July 12, 2016Assignee: Renesas Electronics CorporationInventors: Shinya Suzuki, Kiichi Makuta
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Publication number: 20150279800Abstract: A semiconductor device includes a main structure, active bumps and dummy bumps which are provided over a surface of the main structure. The active bumps are arranged in first to n-th rows. The active bumps positioned in each row are arrayed in a first direction with a predetermined first pitch. The first to n-th rows of the active bummps are arrayed in a second direction perpendicular to the first direction. For j being any integer from one to n?1 a (j+1)-th row are shifted in the second direction from a j-th row of the active bumps by a second pitch and shifted in the first direction from the j-th row of the active bumps by a predetermined sub-pitch. The dummy bumps are arrayed in the first direction with the first pitch, and the length of each of the dummy bumps in the second direction is longer than the second pitch.Type: ApplicationFiled: March 30, 2015Publication date: October 1, 2015Inventors: Shinya SUZUKI, Kiichi MAKUTA
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Publication number: 20150255452Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: ApplicationFiled: May 14, 2015Publication date: September 10, 2015Inventors: Shinya SUZUKI, Kiichi MAKUTA
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Patent number: 9082370Abstract: Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.Type: GrantFiled: October 29, 2013Date of Patent: July 14, 2015Assignee: SYNAPTICS DISPLAY DEVICES GKInventors: Iori Shiraishi, Kiichi Makuta, Satoshi Saito, Masaru Iizuka
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Publication number: 20150124006Abstract: A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.Type: ApplicationFiled: November 5, 2014Publication date: May 7, 2015Inventors: Yoshinori URA, Kiichi MAKUTA, Toshikazu ARAI, Jun UCHIDA, Keita TSUBAKINO
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Publication number: 20150022562Abstract: A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.Type: ApplicationFiled: July 15, 2014Publication date: January 22, 2015Inventors: Keita Tsubakino, Kiichi Makuta, Toshikazu Arai, Yoshinori Ura
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Publication number: 20140118300Abstract: Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.Type: ApplicationFiled: October 29, 2013Publication date: May 1, 2014Applicant: Renesas SP Drivers Inc.Inventors: Iori Shiraishi, Kiichi Makuta, Satoshi Saito, Masaru Iizuka
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Publication number: 20140008793Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: ApplicationFiled: September 17, 2013Publication date: January 9, 2014Applicant: Renesas Electronics CorporationInventors: Shinya Suzuki, Kiichi Makuta
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Patent number: 8564127Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: GrantFiled: June 3, 2010Date of Patent: October 22, 2013Assignee: Renesas Electronics CorporationInventors: Shinya Suzuki, Kiichi Makuta
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Publication number: 20110018129Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.Type: ApplicationFiled: June 3, 2010Publication date: January 27, 2011Applicant: Renesas Electronics CorporationInventors: Shinya Suzuki, Kiichi Makuta
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Patent number: 7376015Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: August 5, 2005Date of Patent: May 20, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Publication number: 20050265114Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: ApplicationFiled: August 5, 2005Publication date: December 1, 2005Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri