Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract: A semiconductor memory is designed to avoid a situation that the program cannot escape from a writing operation, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory has a voltage detecting circuit for detecting whether a boosted voltage has reached a predetermined potential and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential or when it is detected that the predetermined time has elapsed since the start of the boosting operation.

Abstract: Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory having an internal booster has a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time.

Abstract: Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory having an internal booster has a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time.

Abstract: Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory having an internal booster has a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time.

Abstract: The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal.

Abstract: There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse.

Abstract: A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.