Abstract: An automated gas supply system includes a gas cylinder transfer unit configured to transfer a cradle in which one or more gas cylinders storing a gas therein are stored; a gas cylinder inspection unit configured to check properties of the gas stored in the gas cylinder transferred from the gas cylinder transfer unit and check whether the gas leaks from the gas cylinder; a storage queue configured to receive the gas cylinder from the gas cylinder inspection unit by a mobile robot and configured to classify and store the transferred gas cylinders according to the properties of the gas stored in the gas cylinder; and a gas cabinet configured to receive the gas cylinder from the storage queue by the mobile robot and fasten a gas pipe, which is connected to a semiconductor manufacturing process line, to a gas spray nozzle, which is disposed at one side of the received gas cylinder, to supply the gas stored in the gas cylinder to the semiconductor manufacturing process line, wherein the gas cabinet includes a resid

Abstract: A processor implemented method including outputting guide information to guide a capture of an image of a predetermined area via a camera of a mobile terminal including the processor, inputting a first exterior image of a vehicle, the first exterior image being captured based on the output guide information and a second exterior image of the vehicle stored in advance to a processor including a deep learning model, matching the first exterior image and the second exterior image with each other to acquire a matched image, masking a detected area from the predetermined image within the matched image as a masked area, and determining whether an exterior of the vehicle has been damaged and a type of damage based on the masked area.

Abstract: A system and method for providing a traffic accident handling service for a traffic accident are disclosed, where the method includes acquiring state information of a personal mobility device via a sensor and a camera of the personal mobility device, analyzing the traffic accident based on the acquired state information, receiving accident handling information corresponding to the traffic accident, and providing accident handling guide information based on the accident handling information.

Abstract: A method for decoding an image based on an intra prediction, comprising: obtaining a first prediction pixel of a first region in a current block by using a neighboring pixel adjacent to the current block; obtaining a second prediction pixel of a second region in the current block by using the first prediction pixel of the first region; and decoding the current block based on the first and the second prediction pixels.

Abstract: The present disclosure relates to an electronic device, and more specifically, to an electronic device including a printed circuit board including a heat-generating element arranged on one surface thereof, and a heat transfer coin provided such that one surface of the heat transfer coin comes into contact with a portion of the other surface of the printed circuit board, opposite to the heat-generating element, so as to dissipate heat generated from the heat-generating element. Accordingly, the present disclosure provides an advantage of improving heat dissipation performance without increasing the thickness of the printed circuit board.

Abstract: A communication apparatus is provided to include an apparatus enclosure that includes a substrate seating surface and at least one or more connection grooves formed on the substrate seating surface, a first printed circuit board disposed on the substrate seating surface, a second printed circuit board disposed on the substrate seating surface on one side of the first printed circuit board, and at least one or more connectors disposed within the connection groove and configured to electrically connect the first printed circuit board and the second printed circuit board.

Abstract: An apparatus and a method for providing a haptic control signal of a haptic device are disclosed. The apparatus for providing a haptic control signal of a haptic device comprises: a haptic pattern data determination unit for determining haptic pattern data on the basis of at least one of an audio signal and an additional effect signal; a haptic control signal generation unit for generating a haptic control signal for controlling a vibration operation of the haptic device on the basis of the haptic pattern data; and a transmission unit for transmitting the haptic control signal to the haptic device.

Abstract: A display device includes a display panel including a plurality of pixels, a folding area, a first non-folding area disposed on one side of the folding area, and a second non-folding area disposed on the other side of the folding area, a first adhesive layer disposed on one surface of the display panel, and a code pattern layer. The code pattern layer includes a light absorption layer disposed on one surface of the first adhesive layer, a base layer disposed on the light absorption layer, and a plurality of code patterns disposed on the base layer. A thickness of the base layer is smaller than a thickness of the first adhesive layer.

Abstract: A method and device for transmitting a reference signal are discussed. The method can be performed by a wireless device, and can include generating a pseudo-random sequence, generating a reference signal based on the pseudo-random sequence, and transmitting the reference signal sequence. The device can include a signal generator coupled with a data processor and configured to generate a pseudo-random sequence and a reference signal based on the pseudo-random sequence. The device can further include a transmit circuitry configured to transmit the reference signal sequence.

Abstract: A fuel cell vehicle includes a cell stack, a DC level converter, an output unit, a first switching unit disposed between a positive output terminal of the DC level converter and a positive input terminal of the output unit, a second switching unit disposed between a negative output terminal of the DC level converter and a negative input terminal of the output unit, a resistor and a third switching unit connected to each other in series between the positive output terminal of the DC level converter and the negative output terminal of the DC level converter, a fourth switching unit disposed between a contact point between the resistor and the third switching unit and the positive input terminal of the output unit, and a controller for controlling switching operation of the first, second, third and fourth switching units according to an operation mode.

Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

Abstract: A self-healing alloy contains 5 to 11% by weight of molybdenum (Mo), iron (Fe) as a remainder, and unavoidable impurities. A method for manufacturing the self-healing alloy includes heat treating the alloy or preparing an alloy raw material powder and sintering, homogenizing, and cooling the alloy raw material powder.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: A method of transmitting uplink signals is disclosed. The method includes transmitting, by a user equipment, periodic control information on a Physical Uplink Control Channel (PUCCH) at a predetermined period, dropping the periodic control information and multiplexing uplink signals except the periodic control information when the user equipment is operating in subframe bundling transmission mode where the uplink signals are transmitted in a plurality of consecutive subframes, and transmitting the multiplexed uplink signals on a Physical Uplink Shared Channel (PUSCH).