Patents by Inventor Kikuko Sugimae
Kikuko Sugimae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978501Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.Type: GrantFiled: June 16, 2022Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventors: Akiyuki Murayama, Kikuko Sugimae, Katsuya Nishiyama, Yusuke Arayashiki, Motohiko Fujimatsu, Kyosuke Sano, Noboru Shibata
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Patent number: 11972796Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: GrantFiled: October 5, 2022Date of Patent: April 30, 2024Assignee: KIOXIA CORPORATIONInventors: Kikuko Sugimae, Yusuke Arayashiki
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Publication number: 20230253029Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.Type: ApplicationFiled: June 16, 2022Publication date: August 10, 2023Applicant: Kioxia CorporationInventors: Akiyuki MURAYAMA, Kikuko SUGIMAE, Katsuya NISHIYAMA, Yusuke ARAYASHIKI, Motohiko FUJIMATSU, Kyosuke SANO, Noboru SHIBATA
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Publication number: 20230024213Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: ApplicationFiled: October 5, 2022Publication date: January 26, 2023Applicant: Kioxia CorporationInventors: Kikuko SUGIMAE, Yusuke ARAYASHIKI
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Patent number: 11495292Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: GrantFiled: March 9, 2021Date of Patent: November 8, 2022Assignee: Kioxia CorporationInventors: Kikuko Sugimae, Yusuke Arayashiki
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Patent number: 11423997Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.Type: GrantFiled: March 15, 2021Date of Patent: August 23, 2022Assignee: KIOXIA CORPORATIONInventors: Akiyuki Murayama, Kikuko Sugimae, Katsuya Nishiyama, Motohiko Fujimatsu, Noboru Shibata
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Publication number: 20220084609Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.Type: ApplicationFiled: March 15, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Akiyuki MURAYAMA, Kikuko SUGIMAE, Katsuya NISHIYAMA, Motohiko FUJIMATSU, Noboru SHIBATA
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Publication number: 20210391344Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki KUTSUKAKE, Kikuko SUGIMAE, Takeshi KAMIGAICHI
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Patent number: 11133323Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.Type: GrantFiled: November 30, 2018Date of Patent: September 28, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
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Publication number: 20210264976Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: ApplicationFiled: March 9, 2021Publication date: August 26, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kikuko SUGIMAE, Yusuke ARAYASHIKI
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Patent number: 10971225Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: GrantFiled: August 8, 2019Date of Patent: April 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kikuko Sugimae, Yusuke Arayashiki
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Publication number: 20190362786Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: ApplicationFiled: August 8, 2019Publication date: November 28, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kikuko SUGIMAE, Yusuke ARAYASHIKI
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Patent number: 10410717Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: GrantFiled: September 14, 2016Date of Patent: September 10, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kikuko Sugimae, Yusuke Arayashiki
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Publication number: 20190103412Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.Type: ApplicationFiled: November 30, 2018Publication date: April 4, 2019Applicant: Toshiba Memory CorporationInventors: Hiroyuki KUTSUKAKE, Kikuko Sugimae, Takeshi Kamigaichi
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Patent number: 10170489Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.Type: GrantFiled: November 18, 2016Date of Patent: January 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
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Patent number: 9779808Abstract: A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.Type: GrantFiled: September 12, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Arayashiki, Kikuko Sugimae, Reika Ichihara
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Publication number: 20170256310Abstract: A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.Type: ApplicationFiled: September 12, 2016Publication date: September 7, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusuke ARAYASHIKI, Kikuko SUGIMAE, Reika ICHIHARA
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Publication number: 20170256312Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.Type: ApplicationFiled: September 14, 2016Publication date: September 7, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kikuko SUGIMAE, Yusuke ARAYASHIKI
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Patent number: 9679644Abstract: A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.Type: GrantFiled: August 25, 2015Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Miyazaki, Reika Ichihara, Kikuko Sugimae, Yoshihisa Iwata
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Publication number: 20170140818Abstract: A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.Type: ApplicationFiled: February 1, 2017Publication date: May 18, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kikuko SUGIMAE, Reika ICHIHARA