Patents by Inventor Kikuo Kusukawa

Kikuo Kusukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5772780
    Abstract: An organic insulating film is polished utilizing a polishing agent containing cerium oxide particles (a ceria slurry). The ceria slurry is composed of cerium oxide powder containing a total concentration of Na, Ca, Fe, and Cr of less than 10 ppm. Fragile inorganic and organic insulating films formed at relatively low temperatures can be polished without degrading characteristics of a semiconductor element having such films thereon, due to, e.g., Na diffusion.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: June 30, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Homma, Kikuo Kusukawa, Shigeo Moriyama, Masayuki Nagasawa
  • Patent number: 5609511
    Abstract: Disclosed is a method of polishing a thin film layer to be polished, which is formed on the surface of a substrate, by pressing the substrate on the surface of a polishing pad and relatively moving the substrate and the polishing pad, the method comprising the steps of: detecting the position of a front surface of the thin film layer to be polished using a first sensor and also detecting the position of a bottom surface of the thin film layer using a second sensor, on the way of the polishing; calculating the residual thickness of the thin film layer on the basis of the detected positions of the front and bottom surfaces of the thin film layer; and controlling the processing condition of the subsequent polishing on the basis of the calculated residual thickness of the thin film layer.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: March 11, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Moriyama, Yoshio Kawamura, Yoshio Homma, Kikuo Kusukawa, Takeshi Furusawa
  • Patent number: 4984038
    Abstract: The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
    Type: Grant
    Filed: May 17, 1988
    Date of Patent: January 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Makoto Ohkura, Masanobu Miyao, Kikuo Kusukawa, Masahiro Moniwa, ShinIchiro Kimura, Terunori Warabisako, Tokuo Kure
  • Patent number: 4937641
    Abstract: The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
    Type: Grant
    Filed: August 3, 1987
    Date of Patent: June 26, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Makoto Ohkura, Masanobu Miyao, Kikuo Kusukawa, Masahiro Moniwa, ShinIchiro Kimura, Terunori Warabisako, Tokuo Kure