Abstract: A semiconductor device includes a power MOSFET including a trench formed on a surface of a semiconductor layer forming a drain; a gate electrode formed in the trench via a gate insulation film and made of poly-silicon; a channel diffusion layer formed at a surface side of the semiconductor layer shallower than the trench by neighboring the trench; and a source diffusion layer formed at a surface side of the channel diffusion layer by neighboring the trench; wherein a reverse impurity layer is provided at a bottom part side of the trench of the poly-silicon forming the gate electrode; and an impurity ion that is a conductive type opposite to the conductive type of an impurity ion provided in the poly-silicon at a surface side of the trench is provided in the reverse impurity layer.

Abstract: A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

Abstract: A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

Abstract: A semiconductor device includes a power MOSFET including a trench formed on a surface of a semiconductor layer forming a drain; a gate electrode formed in the trench via a gate insulation film and made of poly-silicon; a channel diffusion layer formed at a surface side of the semiconductor layer shallower than the trench by neighboring the trench; and a source diffusion layer formed at a surface side of the channel diffusion layer by neighboring the trench; wherein a reverse impurity layer is provided at a bottom part side of the trench of the poly-silicon forming the gate electrode; and an impurity ion that is a conductive type opposite to the conductive type of an impurity ion provided in the poly-silicon at a surface side of the trench is provided in the reverse impurity layer.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, and a fuse element. The semiconductor substrate includes main and back surfaces and a trimming opening penetrating therethrough from the back surface to the main surface. The insulating film is formed on the semiconductor substrate. The fuse element is formed on the main surface of the semiconductor substrate through the insulating film at a position facing the trimming opening. A method of manufacturing a semiconductor device includes the steps of forming a fuse element and forming a trimming opening. The forming step forms the fuse element on a main surface of a semiconductor substrate through an insulating film. The forming step forms the trimming opening from a back surface of the semiconductor substrate to the main surface of the semiconductor substrate at a position facing the fuse element after a formation of the fuse element.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, and a fuse element. The semiconductor substrate includes main and back surfaces and a trimming opening penetrating therethrough from the back surface to the main surface. The insulating film is formed on the semiconductor substrate. The fuse element is formed on the main surface of the semiconductor substrate through the insulating film at a position facing the trimming opening. A method of manufacturing a semiconductor device includes the steps of forming a fuse element and forming a trimming opening. The forming step forms the fuse element on a main surface of a semiconductor substrate through an insulating film. The forming step forms the trimming opening from a back surface of the semiconductor substrate to the main surface of the semiconductor substrate at a position facing the fuse element after a formation of the fuse element.

Abstract: A method of determining the amount of exposure is provided, in which a projection exposure is carried out onto a photoresist film using a photomask, having a plurality of openings with transmittance values different from one opening to the next stepwise, and through which light beams are irradiated for the exposure. Subsequently, the openings from which the photoresist is completely removed are observed and a lowest light transmittance value is found among the corresponding openings, to thereby the minimum amount of the exposure E.sub.th for removing the photoresist film is determined. The minimum amount of the projection exposure is found by exposing a plurality of portions with a single exposure step, and the determination of amount of the exposure becomes feasible with relative ease.