Patents by Inventor Kikuo Sakai

Kikuo Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5181983
    Abstract: An adhesive tape cutting device rotatably supporting an adhesive tape roll, which is adapted to adhere an adhesive tape of a desired length on a surface of an object, and is capable of reliably and repeatedly delivering the next tip of the tape from the adhesive tape roll for the next adhesion operation. The device comprises a lever movably mounted on the base member; a pressing surface portion, which is formed on a bottom portion of the lever for pressing the upper surface of the adhesive tape at the time of adhering the tape; an arm member provided on a portion of the lever for temporarily fixing a delivered portion of the tape on a temporary fixing member mounted on the base member; and a blade mounted on the lever for cutting a free end portion of the tape. It is possible to perform operations of adhering and cutting by simply displacing the lever relative to a guiding edge formed on the bottom of the base member.
    Type: Grant
    Filed: June 19, 1991
    Date of Patent: January 26, 1993
    Assignee: Shinwa Denshi Kabushiki Kaisha
    Inventor: Kikuo Sakai
  • Patent number: 4912674
    Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.
    Type: Grant
    Filed: February 14, 1989
    Date of Patent: March 27, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Youichi Matsumoto, Ryuuji Shibata, Isamu Kobayashi, Satoshi Meguro, Kouichi Nagasawa, Hideo Meguro, Hisahiro Moriuchi, Masahiro Ogata, Kikuo Sakai, Toshifumi Takeda
  • Patent number: 4848022
    Abstract: The handle for a fishing rod according to the present invention can improve the sense of fit of the fingers with respect to a reel-attaching portion when said portion is taken hold of. The handle comprises a reel-depositing surface of the reel-attaching portion expanded in both right and left directions to form a bulgy portion which makes the width of said surface larger than that of a reel-foot. In accordance with the reel-depositing surface, the finger-placing surface of the reel-attaching portion is formed to have a large circular surface area which fits well with the dispositions and the bending angle of the fingers. This configulation is very advantageous in giving an improved sense of fit of the fingers with respect to the finger-placing surface of the reel-attaching portion and also a comfortable and safe gripping performance.
    Type: Grant
    Filed: November 22, 1988
    Date of Patent: July 18, 1989
    Assignee: Daiwa Seiko, Inc.
    Inventors: Takafumi Ozeki, Kikuo Sakai, Noriyasu Fukushima
  • Patent number: 4839860
    Abstract: A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other.
    Type: Grant
    Filed: January 17, 1986
    Date of Patent: June 13, 1989
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Takashi Shinoda, Kikuo Sakai, Masahiro Ogata, Hiroshi Kawamoto, Yoshiaki Onishi, deceased, by Junko Onishi, administratrix
  • Patent number: 4805143
    Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.
    Type: Grant
    Filed: January 12, 1987
    Date of Patent: February 14, 1989
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Youichi Matsumoto, Ryuuji Shibata, Isamu Kobayashi, Satoshi Meguro, Kouichi Nagasawa, Hideo Meguro, Hisahiro Moriuchi, Masahiro Ogata, Kikuo Sakai, Toshifumi Takeda
  • Patent number: 4780875
    Abstract: A semiconductor memory incorporating an ECC circuit includes a memory array, means for selecting a plurality of bits which are to be simultaneously output to the outside of the IC from a plurality of bits which are simultaneously read out from the memory array, and an error correcting circuit which constitutes the ECC circuit. The selecting means is provided in a stage previous to the error correcting circuit. In consequence, it is possible to reduce the number of bits of a signal which need to be simultaneously processed by the error correcting circuit. Accordingly, the size of the ECC circuit can be reduced.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: October 25, 1988
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventor: Kikuo Sakai
  • Patent number: 4604749
    Abstract: YA semiconductor memory is provided with memory cells for storing a plurality of sets of data, each of the sets having check bits. A selecting circuit selects some of the memory cells to form a set in response to a first address signal. The circuit includes an error correcting code circuit, a tristate circuit and a control circuit which forms a control signal to control the tristate circuit. Output terminals of the tristate circuit are coupled with external output terminals of the semiconductor memory. Also, the tristate circuit is controlled by the control signal to bring the external circuit terminals into high impedance at least during the time when the error correcting code circuit is delivering indefinite data.
    Type: Grant
    Filed: June 9, 1983
    Date of Patent: August 5, 1986
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Takashi Shinoda, Kikuo Sakai, Masahiro Ogata, Hiroshi Kawamoto, Yoshiaki Onishi, deceased, Junko Onishi, administratrix
  • Patent number: 4592024
    Abstract: The address of each defective memory cell in a memory cell array is stored within a semiconductor ROM in advance. In parallel with the operation of reading out information from a memory cell of the array, whether or not the address of the memory cell agrees with the previously stored address of a defective memory cell is distinguished. When they agree, a correcting signal is formed. Erroneous data read out from the defective memory cell is inverted on the basis of the correcting signal and thus corrected, whereupon the corrected data is delivered out of the ROM. In using this error data correcting system, a read-out access time delay caused by furnishing the correcting function corresponds to only one stage of a logic circuit which is used for the inversion to correct the erroneous data. Thus, a semiconductor ROM furnished with an error correcting function can be provided without spoiling enhancement in the speed of the read-out operation.
    Type: Grant
    Filed: July 1, 1983
    Date of Patent: May 27, 1986
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Kikuo Sakai, Yoshiaki Onishi, deceased, by Junko Onishi, administratrix