Patents by Inventor Kil-Soo Kim
Kil-Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038727Abstract: A semiconductor package and method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip including first and second surfaces opposite to each other; connection terminals on the first surface of the first semiconductor chip; a first dielectric layer on the second surface of the first semiconductor chip; a second semiconductor chip on the first dielectric layer and including a third surface opposite to the second surface and a fourth surface opposite to the third surface; a second dielectric layer on the third surface of the second semiconductor chip and in contact with the first dielectric layer; a third semiconductor chip on the fourth surface of the second semiconductor chip; and a first adhesive layer between the second semiconductor chip and the third semiconductor chip, the first dielectric layer and the second dielectric layer including no wirings.Type: ApplicationFiled: June 26, 2023Publication date: February 1, 2024Applicant: Samsung Electronics Co., Ltd.Inventor: Kil Soo KIM
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Publication number: 20220216193Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventor: Kil-soo KIM
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Patent number: 11309280Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: GrantFiled: July 8, 2020Date of Patent: April 19, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
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Patent number: 11309300Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.Type: GrantFiled: August 1, 2018Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kil-soo Kim
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Patent number: 11205637Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: GrantFiled: September 2, 2020Date of Patent: December 21, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Won-keun Kim, Kyung-suk Oh, Ji-han Ko, Kil-soo Kim, Yeong-seok Kim, Joung-phil Lee, Hwa-il Jin, Su-jung Hyung
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Publication number: 20200402952Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Won-keun KIM, Kyung-suk OH, Ji-han KO, Kil-soo KIM, Yeong-seok KIM, Joung-phil LEE, Hwa-il JIN, Su-jung HYUNG
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Publication number: 20200343219Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: ApplicationFiled: July 8, 2020Publication date: October 29, 2020Inventors: Yong-hoon KIM, Kil-soo KIM, Kyung-suk OH, Tae-joo HWANG
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Patent number: 10797021Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: GrantFiled: April 12, 2019Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Won-keun Kim, Kyung-suk Oh, Ji-han Ko, Kil-soo Kim, Yeong-seok Kim, Joung-phil Lee, Hwa-il Jin, Su-jung Hyung
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Patent number: 10727199Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: GrantFiled: June 7, 2018Date of Patent: July 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
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Patent number: 10699983Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.Type: GrantFiled: November 14, 2018Date of Patent: June 30, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kil-soo Kim, Yong-hoon Kim, Hyun-ki Kim, Kyung-suk Oh
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Publication number: 20200075545Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: ApplicationFiled: April 12, 2019Publication date: March 5, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Won-keun KIM, Kyung-suk Oh, Ji-han Ko, Kil-soo Kim, Yeong-seok Kim, Joung-phil Lee, Hwa-il Jin, Su-jung Hyung
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Publication number: 20190295917Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.Type: ApplicationFiled: November 14, 2018Publication date: September 26, 2019Inventors: Kil-soo KIM, Yong-hoon KIM, Hyun-ki KIM, Kyung-suk OH
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Publication number: 20190148349Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.Type: ApplicationFiled: August 1, 2018Publication date: May 16, 2019Inventor: Kil-soo KIM
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Publication number: 20190148337Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.Type: ApplicationFiled: June 7, 2018Publication date: May 16, 2019Inventors: Yong-hoon KIM, Kil-soo KIM, Kyung-suk OH, Tae-joo HWANG
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Publication number: 20170243855Abstract: A semiconductor package including a mounting board, a first semiconductor chip on the mounting board, the first semiconductor chip having a first peripheral area, a second peripheral area, and a central area between the first and second peripheral areas, the central area having penetrating electrodes formed therein, a second semiconductor chip on the first peripheral area, the second semiconductor chip including a second pad on a top surface thereof, a third semiconductor chip on the second peripheral area, the third semiconductor chip including a third pad on a top surface thereof, and conductive wirings extending from the second and third pads, respectively, the conductive wirings electrically connected to the penetrating electrodes, respectively, may be provided.Type: ApplicationFiled: November 11, 2016Publication date: August 24, 2017Applicant: Samsung Electronics Co., Ltd.Inventor: Kil Soo KIM
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Patent number: 9691737Abstract: Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.Type: GrantFiled: March 3, 2015Date of Patent: June 27, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kil-Soo Kim
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Patent number: 9299685Abstract: A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.Type: GrantFiled: August 5, 2014Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kil-Soo Kim
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Publication number: 20150357310Abstract: Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.Type: ApplicationFiled: March 3, 2015Publication date: December 10, 2015Inventor: Kil-Soo KIM
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Patent number: 9072525Abstract: Provided is a combinable electrode needle base structure in which a base to which electrode needles are coupled can be used in a combined or separated state to use the electrode needles according to the size and location of a lesion. In the combinable electrode needle structure, electrode needles are connected to the front side of an electrode needle base, and receive RF waves from RF (radio frequency) generator. The electrode needle base is divided into dividable bases to which the electrode needles are respectively coupled. When a lesion to be cauterized is large or cauterization should be concentrated, the dividable bases are combined and then used, and when a lesion is small or lesions are scattered, the dividable bases may be separated and then used.Type: GrantFiled: January 21, 2011Date of Patent: July 7, 2015Assignees: Taewoong Medical Co., Ltd.Inventors: Kyung-Min Shin, Kyung-Hoon Shin, Kil-Soo Kim, Dong-Un Kim
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Publication number: 20150035142Abstract: A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.Type: ApplicationFiled: August 5, 2014Publication date: February 5, 2015Inventor: Kil-Soo KIM