Patents by Inventor Kil-Sub Roh

Kil-Sub Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package
    Patent number: 6080931
    Abstract: A semiconductor package is disclosed, including: (a) two semiconductor chips having a plurality of bonding pads; (b) an insulating circuit film having (i) an insulating base film with a plurality of through holes, (ii) a plurality of first metal lines formed on upper and lower faces of the base film, (iii) a plurality of protruding, conductive inner pads which are respectively formed on the first metal lines, being respectively connected to said bonding pads of each semiconductor chip, (iv) a plurality of protruding, conductive outer pads which are formed on the first metal line at a predetermined interval from the plurality of inner pads, and (v) a plurality of second metal lines formed along wall surface of the plurality of through holes to connect to the inner pads of each semiconductor chip, for electrically connecting inner pads each other which are positioned at the upper and lower surfaces of the base film, (c) a lead frame including an inner lead for connecting the outer pads of the insulating circuit
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: June 27, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kyei Chan Park, Kil-Sub Roh
  • Multi-layer bottom lead package
    Patent number: 5834836
    Abstract: A multi-layer bottom lead package of the present invention has semiconductor chips having: (a) bonding pads; (b) an insulating circuit film including (i) an insulating base film with through holes, (ii) first metal lines formed on upper and lower faces of the base film, (iii) protruding, conductive inner pads which are respectively formed on the first metal lines, being respectively connected to said bonding pads of each semiconductor chip, (iv) protruding, conductive outer pads which are formed on the first metal line, and (v) second metal lines formed along wall surface of the through holes to connect to the inner pads of each semiconductor chip; (c) a lead frame including an inner lead and outer lead for electrically connecting the outer pads of the insulating circuit film to an external device; and (d) a package body of encapsulating a predetermined area containing the semiconductor chips, the insulating circuit film and the inner leads of the lead frame, including a plurality of dimples formed at electri
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: November 10, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kyei Chan Park, Kil-Sub Roh