Patents by Inventor Kil Su JUNG

Kil Su JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489041
    Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 1, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Kil Su Jung, Keun Heo, Sung Jun Kim
  • Patent number: 11437572
    Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Kil Su Jung, Keun Heo
  • Publication number: 20210005710
    Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: January 7, 2021
    Applicant: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong PARK, Kil Su JUNG, Keun HEO, Sung Jun KIM
  • Publication number: 20200357988
    Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 12, 2020
    Applicant: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong PARK, Kil Su JUNG, Keun HEO