Abstract: A display controller includes a resource controller configured to receive layer information about each of a first layer and a second layer that are output at different times through a display panel during a unit frame. The display controller includes a data input direct memory access (DMA) configured to receive first image data corresponding to the first layer and second image data corresponding to the second layer, and a hardware resource configured to receive the first and second image data from the data input DMA, process the received first and second image data according to the layer information, and generate first layer data of the first layer and second layer data of the second layer. The resource controller is configured to control the data input DMA according to the layer information to determine an order in which the first and second image data are provided to the hardware resource.

Abstract: A system on chip and a mobile device are provided. The mobile device comprises a processor configured to receive raw image data, process the raw image data into floating-point format image data, and output the floating-point format image data, a memory configured to store therein the floating-point format image data, and a display processing unit configured to receive the floating-point format image data stored in the memory therefrom, and perform high dynamic range (HDR) processing on the floating-point format image data.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Abstract: A graphic processing unit, a graphic processing system comprising the same, and a rendering method using the same. The graphic processing unit includes a geometry processing unit configured to receive a vertex and to output a primitive and information about texture patches corresponding to the primitive using the vertex, and a rendering processing unit configured to convert the output primitive into a fragment and to perform fragment shading on the converted fragment, wherein the texture patch indexed by the texture patch information is pre-loaded to the rendering processing unit before the fragment shading is performed.

Abstract: A tessellation method includes assigning a tessellation factor to each of a plurality of points in a patch and generating, in the vicinity of a first point of the plurality of points, at least one new point based on a first tessellation factor assigned to the first point. The at least one first new point corresponds to the first point.

Abstract: A method of operating a graphics processing unit includes determining, based on input data, whether to perform a tiling operation before or after a tessellation operation and performing the tiling operation according to the determination result. Performing the tiling operation after the tessellation operation if the input data is not a patch, and if a geometry of the patch is at the out-side of a convex hull defined by control points of the patch. Performing the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to the patch changes according to a shading operation.

Abstract: A method of generating tessellation data include analyzing patch data of each of a plurality of patches; generating shared data that is shared by the patches, non-shared data that are not shared by the patches, and attribute data on an attribute of control points of each of the patches from the patch data according to a result of the analyzing; and compressing the non-shared data and the attribute data.

Abstract: A compositor selects a subset of image layers from a plurality of image layers with which to form an intermediate image. The compositor forms a resultant image from an intermediate image and one or more remaining image layers.

Abstract: A method for multi image layer composition includes dividing a frame buffer into tile areas, for each the area, determining image layers to be composited, for each tile area, generating a composite image layer by compositing its determined image layers, and merging the composite image layers into an overall composite image layer, wherein generating the composite image layers for at least one of the tiles comprises reading image layer information of the image layers from a top image layer to a bottom image layer, determining whether to read a lower image layer using the information of the image layers thereabove, if the lower image layer is determined not to be read, defining the image layer above the lower image layer as an effective bottom image layer, and compositing the effective bottom image layer with upper image layers, and not compositing the effective bottom image layer with an image layer thereunder.

Abstract: A method of operating a graphics processing unit includes determining, based on input data, whether to perform a tiling operation before or after a tessellation operation and performing the tiling operation according to the determination result. Performing the tiling operation after the tessellation operation if the input data is not a patch, and if a geometry of the patch is at the out-side of a convex hull defined by control points of the patch. Performing the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to the patch changes according to a shading operation.

Abstract: A method of generating tessellation data include analyzing patch data of each of a plurality of patches; generating shared data that is shared by the patches, non-shared data that are not shared by the patches, and attribute data on an attribute of control points of each of the patches from the patch data according to a result of the analyzing; and compressing the non-shared data and the attribute data.

Abstract: A tessellation method includes assigning a tessellation factor to each of a plurality of points in a patch and generating, in the vicinity of a first point of the plurality of points, at least one new point based on a first tessellation factor assigned to the first point. The at least one first new point corresponds to the first point.