Patents by Inventor Kim B. Roberts

Kim B. Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11652566
    Abstract: In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 16, 2023
    Assignee: CIENA CORPORATION
    Inventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim B. Roberts
  • Publication number: 20230017120
    Abstract: A transmitter generates an encoded vector by encoding a data vector, the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits a signal representing the encoded vector over a communication channel. A receiver determines a vector estimate from the signal and recovers the data vector from the vector estimate by sequentially decoding the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Shahab OVEIS GHARAN, Mohammad Ehsan SEIFI, Kim B. ROBERTS
  • Publication number: 20220321247
    Abstract: A system is configured to measure (602) a forward error correction (FEC) decoding property (216) associated with applying FEC decoding (214) to FEC-encoded bits or symbols at a receiver device (202) deployed in a communication network (100). The system is configured to provide (606) an assessment of operating conditions of the receiver device based on the FEC decoding property. The FEC decoding property comprises, for example, a distribution of a number of iterations of a FEC decoding operation applied to a plurality of FEC blocks processed within a period of time. In some examples, the FEC decoding property comprises any one of heat, temperature, current, voltage, active clock cycles, idle clock cycles, activity of parallel engines, activity of pipeline stages, and input or output buffer fill level of the FEC decoding. The assessment is based, for example, on a comparison between the FEC decoding property and reference FEC data (218).
    Type: Application
    Filed: September 30, 2020
    Publication date: October 6, 2022
    Inventors: Andrew D. SHINER, Shahab OVEIS GHARAN, Michael HUBBARD, Kim B. ROBERTS
  • Patent number: 11239929
    Abstract: A receiver is configured to detect, at a communication interface, a received signal that suffers from degradations incurred over a communication channel. The receiver applies an adaptive filter to a series of received blocks of a digital representation of the received signal, thereby generating respective filtered blocks, where each received block represents 2N frequency bins, and where N is a positive integer. The receiver calculates coefficients for use by the adaptive filter on a jth received block as a function of (i) error estimates associated with an (j?D?1)th filtered block, where D is a positive integer representing a number of blocks, and where j is a positive integer greater than (D?1); and (ii) an inverse of an approximate covariance matrix associated with the (j?D?1)th received block, where the approximate covariance matrix is a diagonal matrix of size L×L, and where L is a positive integer lower than 2N.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: February 1, 2022
    Assignee: Ciena Corporation
    Inventors: Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard, Kim B. Roberts
  • Patent number: 11233568
    Abstract: A receiver is configured to detect, at a communication interface, a received signal that suffers from degradations incurred over a communication channel. The receiver applies an adaptive filter to a series of received blocks of a digital representation of the received signal, thereby generating respective filtered blocks.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: January 25, 2022
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Ramin Babaee, Martin Bouchard, Kim B. Roberts
  • Patent number: 11233523
    Abstract: An apparatus is configured to generate, from a stream of periodic digital samples, a first sub-stream of periodic analog samples and a second sub-stream of periodic analog samples, each sub-stream comprising substantially stable time intervals. The apparatus is further configured to generate a sign-modulated sub-stream by applying to the second sub-stream a sign modulation operation effecting a sign transition during a stable time interval of the second sub-stream. The apparatus is further configured to generate an output stream of periodic analog samples based on a sum of the first sub-stream and the sign-modulated sub-stream, wherein a period of the output stream is shorter than periods of the first and second sub-streams.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 25, 2022
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Ian Roberts, Yuriy Greshishchev, Naim Ben-Hamida, Kim B. Roberts
  • Patent number: 11201695
    Abstract: A method performed at an electronic device comprises receiving information bits, a first nub, and a second nub, each nub comprising redundant values; calculating first calculated determiners from first subsets of the information bits along a first dimension; calculating first corrected determiners by applying first FEC decoding to a combination of the first calculated determiners and the first nub; correcting at least one error in the information bits using a difference between the first corrected determiners and the first calculated determiners; calculating second calculated determiners from second subsets of the information bits along a second dimension that differs from the first dimension; calculating second corrected determiners by applying second FEC decoding to a combination of the second calculated determiners and the second nub; and correcting at least one additional error in the information bits using a difference between the second corrected determiners and the second calculated determiners.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: December 14, 2021
    Assignee: CIENA CORPORATION
    Inventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim B. Roberts
  • Patent number: 11171661
    Abstract: A controlled switch having N inputs and a single output (N?2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Yuriy Greshishchev, Naim Ben-Hamida, Kim B. Roberts
  • Patent number: 11126219
    Abstract: A receiver apparatus comprises circuitry configured for storing a first sequence of values. At the receiver apparatus, a communications signal is received which conveys a second sequence of values, the second sequence of values being related to the first sequence of values. According to some examples, the second sequence of values is identical to the first sequence of values. At the receiver apparatus, P results are calculated from a cross-correlation of the first sequence of values with at least a portion of a representation of the communications signal, where P is a positive integer. According to some examples, P?2. An estimate of a phase offset of a continuous clock is calculated as a function of the P results. According to some examples, the function is a non-linear function. The estimate of the clock phase offset may be used to achieve clock recovery at the receiver apparatus.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 21, 2021
    Assignee: CIENA CORPORATION
    Inventors: Shahab Oveis Gharan, Kim B. Roberts
  • Patent number: 11082157
    Abstract: A system is configured to measure a forward error correction (FEC) decoding property associated with applying FEC decoding to FEC-encoded bits or symbols at a receiver device deployed in a communication network. The system is further configured to provide an assessment of operating conditions of the receiver device based on the FEC decoding property. In one example, the FEC decoding property comprises a distribution of a number of iterations of a FEC decoding operation applied to a plurality of FEC blocks processed within a period of time. In some examples, the FEC decoding property comprises any one of heat, temperature, current, voltage, active clock cycles, idle clock cycles, activity of parallel engines, activity of pipeline stages, and input or output buffer fill level of the FEC decoding. In some examples, the assessment is based on a comparison between the FEC decoding property and reference FEC data.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 3, 2021
    Assignee: CIENA CORPORATION
    Inventors: Andrew D. Shiner, Shahab Oveis Gharan, Michael Hubbard, Kim B. Roberts
  • Publication number: 20210234634
    Abstract: A method performed at an electronic device comprises receiving information bits, a first nub, and a second nub, each nub comprising redundant values; calculating first calculated determiners from first subsets of the information bits along a first dimension; calculating first corrected determiners by applying first FEC decoding to a combination of the first calculated determiners and the first nub; correcting at least one error in the information bits using a difference between the first corrected determiners and the first calculated determiners; calculating second calculated determiners from second subsets of the information bits along a second dimension that differs from the first dimension; calculating second corrected determiners by applying second FEC decoding to a combination of the second calculated determiners and the second nub; and correcting at least one additional error in the information bits using a difference between the second corrected determiners and the second calculated determiners.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 29, 2021
    Applicant: CIENA CORPORATION
    Inventors: Shahab OVEIS GHARAN, Mohammad Ehsan SEIFI, Kim B. ROBERTS
  • Patent number: 11070312
    Abstract: A transmitter generates determiners from data vectors representing payload information, each determiner representing parity information dependent on the payload information. The transmitter encodes the determiners to generate a nub vector representing compressed parity information dependent on the parity information, wherein the encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the determiners and then calculating the nub vector from the codewords, at least one of the codewords being calculated from at least one recursion of a mathematical operation, and at least one of the codewords comprising more than 6 terms. The transmitter transmits signals representing the data vectors and the nub vector to a receiver, where recovery of the data vectors at the receiver involves sequential decoding of the FEC codewords, wherein at least one codeword decoded earlier in the decoding enhances an estimate of at least one codeword decoded later in the decoding.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 20, 2021
    Assignee: CIENA CORPORATION
    Inventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim B. Roberts
  • Publication number: 20210211135
    Abstract: A controlled switch having N inputs and a single output (N?2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 8, 2021
    Inventors: Shahab OVEIS GHARAN, Yuriy GRESHISHCHEV, Naim BEN-HAMIDA, Kim B. ROBERTS
  • Patent number: 11038599
    Abstract: A receiver applies first processing to a digital representation of a received signal to generate a first processed signal having first additive noise and first linear inter-symbol interference (ISI), the first processing comprising a substantially linear operation designed to substantially minimize a sum of variances of the first additive noise and the first linear ISI. The receiver applies second processing to the first processed signal to generate a second processed signal having second additive noise and second linear ISI, the second processing comprising a substantially nonlinear operation designed (i) to make a variance of the second additive noise substantially lower than the variance of the first additive noise, and (ii) to make a sum of the variance of the second additive noise and a variance of the second linear ISI substantially lower than the sum of the variances of the first additive noise and first linear ISI.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: June 15, 2021
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Kim B. Roberts
  • Publication number: 20210126734
    Abstract: A system is configured to measure a forward error correction (FEC) decoding property associated with applying FEC decoding to FEC-encoded bits or symbols at a receiver device deployed in a communication network. The system is further configured to provide an assessment of operating conditions of the receiver device based on the FEC decoding property. In one example, the FEC decoding property comprises a distribution of a number of iterations of a FEC decoding operation applied to a plurality of FEC blocks processed within a period of time. In some examples, the FEC decoding property comprises any one of heat, temperature, current, voltage, active clock cycles, idle clock cycles, activity of parallel engines, activity of pipeline stages, and input or output buffer fill level of the FEC decoding. In some examples, the assessment is based on a comparison between the FEC decoding property and reference FEC data.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Applicant: CIENA CORPORATION
    Inventors: Andrew D. SHINER, Shahab OVEIS GHARAN, Michael HUBBARD, Kim B. ROBERTS
  • Patent number: 10992416
    Abstract: Compression coding may be used with forward error correction (FEC) coding to provide higher information rates by reducing the proportion of redundant bits relative to information bits that are transmitted from a transmitter to a receiver. In one example, first determiners and second determiners are calculated from a set of information bits, where each first determiner is calculated from a different first subset of the information bits along a first dimension, and each second determiner is calculated from a different second subset of the information bits along a second dimension that differs from the first dimension. First and second nubs are calculated from the first and second determiners, respectively, each nub comprising a number of redundant bits that is less than the number of bits in the determiners from which the nub is calculated. The information bits and the nubs are transmitted over one or more communications channels.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 27, 2021
    Assignee: CIENA CORPORATION
    Inventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim B. Roberts
  • Publication number: 20210109563
    Abstract: A receiver apparatus comprises circuitry configured for storing a first sequence of values. At the receiver apparatus, a communications signal is received which conveys a second sequence of values, the second sequence of values being related to the first sequence of values. According to some examples, the second sequence of values is identical to the first sequence of values. At the receiver apparatus, P results are calculated from a cross-correlation of the first sequence of values with at least a portion of a representation of the communications signal, where P is a positive integer. According to some examples, P?2. An estimate of a phase offset of a continuous clock is calculated as a function of the P results. According to some examples, the function is a non-linear function. The estimate of the clock phase offset may be used to achieve clock recovery at the receiver apparatus.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Applicant: CIENA CORPORATION
    Inventors: Shahab OVEIS GHARAN, Kim B. ROBERTS
  • Publication number: 20210083798
    Abstract: A transmitter of a communications system includes a first encoder configured to apply a shaping operation to a data signal to generate a shaped data signal, a second encoder configured to encode the shaped data signal according to a forward error correction (FEC) scheme to generate an encoded signal, and a constellation mapper configured to modulate the encoded signal to symbol values according to a modulation scheme to generate a corresponding symbol stream for transmission through the communications system. The shaping operation reduces average constellation energy for constellations of the modulation scheme.
    Type: Application
    Filed: July 31, 2020
    Publication date: March 18, 2021
    Inventors: Shahab OVEIS GHARAN, Kim B. ROBERTS, Akbar GHASEMI, Mahmoud TAHERZADEHBOROUJENI
  • Patent number: 10938483
    Abstract: An optical signal modulated with a stream of symbols comprising a sequence of training symbols is received at a receiver. First equalizer circuitry calculates and applies first coefficients to digital signals representative of the optical signal, thereby resulting in first compensated signals. Second equalizer circuitry calculates second coefficients based on a correlation between the first compensated signals and digital signals representative of the sequence of training symbols and applies the second coefficients to the first compensated signals, thereby resulting in second compensated signals. Third equalizer circuitry calculates and applies third coefficients to the second compensated signals, thereby resulting in third compensated signals. The first, second, and third coefficients compensate for impairments in the optical signal varying at respective first, second, and third rates, where the third rate is higher than the first rate and lower than the second rate.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: March 2, 2021
    Assignee: CIENA CORPORATION
    Inventors: Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard, Kim B. Roberts
  • Patent number: 10903903
    Abstract: A transmitter (102,200) applies a dimensional transformation to preliminary digital drive signals representing symbols, thereby generating transformed digital drive signals (704) designed to represent each symbol using a plurality of first dimensions of an optical carrier (242), the first dimensions distributed over two or more timeslots. The preliminary digital drive signals are designed to represent each symbol using a plurality of second dimensions of the carrier, which differ from the first dimensions. Using the transformed signals, the transmitter generates (706) an optical signal (260). A receiver (102,300) receives (802) an optical signal (360) and determines received digital signals (804) corresponding to the first dimensions. The receiver applies an inverse dimensional transformation to the received digital signals to generate preliminary digital drive signal estimates (806) corresponding to the second dimensions, thereby permitting estimation of the symbols (808).
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 26, 2021
    Assignee: CIENA CORPORATION
    Inventors: Amir Keyvan Khandani, Shahab Oveis Gharan, Michael Andrew Reimer, Maurice O'Sullivan, Kim B. Roberts