Abstract: An array processing circuit which operates on a M row-N column array of digital words includes a first set of N memories, each of which asynchronously receives a respective column of words from a separate input channel; and, a second set of N memories which have respective inputs that are coupled to corresponding outputs of the first set of memories. A first addressing circuit detects when each memory of the first set contains a respective word of the same row, and in response transfers that row of words in parallel to the second set of memories. N-1 column error detect circuits respectively detect when a column of words from the first N-1 memories of the first set has an error.