Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory having a large aspect ratio serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. The memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory. These global data lines are double data rate and single-ended which increases the physical spacing of these lines thereby reducing capacitance and power requirements. Each of the global data lines are routed to only one of the memory sections. This results in the average length of these lines being less than the length of the entire memory, which reduces the capacitance of the lines.

Abstract: A predecoder circuit for use in association with a memory circuit is shown to have a dynamic NAND gate formed by series-coupled transistors controlled by a bank active select signal and a row address selection signal. The predecoder circuit also includes a precharge circuit coupled to the dynamic NAND gate and controlled by a precharge signal. The predecoder circuit further includes a first inverter having an input terminal electrically coupled to the dynamic NAND gate and an output terminal selectively electrically connectable to at least one row decoder circuit for the memory circuit. The predecoder circuit finally includes a second inverter arranged in feedback with the first inverter to form a latch.

Abstract: A switching circuit incorporating a high voltage transistor protection technique for use in an integrated circuit device having dual voltage supplies which extends the maximum pumped voltage (“VCCP”) for reliable MOS transistor operation to VCCP=VTN+(2*VCC), where VTN is the threshold voltage of the transistor and VCC is the supply voltage level. This is effectuated by adding an additional relatively thick gate oxide transistor in series with the relatively thin gate oxide MOS N-channel transistors in a conventional high voltage switching circuit to increase the reliable maximum voltage for the high voltage power supply.

Abstract: A sense amplifier design for DRAM devices (as well as those incorporating embedded DRAM) which provides improved read and write speed without requiring the use of an extra signal line to the gate of a transistor coupling the sense amplifier latch nodes to the associated bit lines. In accordance with the present invention, an additional circuit element is added between the latch nodes and the bit lines which serves as a resistive path therebetween. Functionally, this additional circuit element serves to isolate the latch nodes from the relatively large bit line capacitance during a write operation such that the latch nodes can change state more quickly. These additional circuit elements may take the form of N-channel transistors having their gate tied to a pumped voltage level VCCP, resistors, various configurations of depletion transistors or CMOS pass gates.

Abstract: A small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays which advantageously utilizes non-precharged data lines and reduced output voltage swing to reduce power requirements, tri-stateable outputs to allow several circuits to be multiplexed on the same data line and provides a buffer between the sense amplifier and the data lines to improve data line switching speed.

Abstract: A negative voltage driver circuit having reduced current flow to the negative supply voltage source and improved reliability comprises first, second and third series coupled switching devices defining an output and intermediate nodes therebetween respectively for coupling a high voltage source to a reference voltage level. Control terminals of the first and second switching devices are coupled to a first circuit node and a control terminal of the third switching device is coupled to a second circuit node. A fourth switching device is coupled between the lower intermediate node and a negative voltage source, with a control terminal of the fourth switching device being coupled to a third circuit node. In operation, the first circuit node is activated, followed sequentially by the second and third circuit nodes, the second circuit node being deactivated substantially concurrently with the activation of the third circuit node.

Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory (“DRAM”) having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. This architecture is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio as well as a relatively large number of input/outputs (“I/Os”) which must be located along one narrow side of the memory. In accordance with the present invention, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory.

Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory (“DRAM”) having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. This architecture is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio as well as a relatively large number of input/outputs (“I/Os”) which must be located along one narrow side of the memory. In accordance with the present invention, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory.

Abstract: A small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays which advantageously utilizes non-precharged data lines and reduced output voltage swing to reduce power requirements, tri-stateable outputs to allow several circuits to be multiplexed on the same data line and provides a buffer between the sense amplifier and the data lines to improve data line switching speed.

Abstract: A switching circuit incorporating a high voltage transistor protection technique for use in an integrated circuit device having dual voltage supplies which extends the maximum pumped voltage (“VCCP”) for reliable MOS transistor operation to VCCP=VTN+(2*VCC), where VTN is the threshold voltage of the transistor and VCC is the supply voltage level. This is effectuated by adding an additional relatively thick gate oxide transistor in series with the relatively thin gate oxide MOS N-channel transistors in a conventional high voltage switching circuit to increase the reliable maximum voltage for the high voltage power supply.

Abstract: A negative voltage driver circuit having reduced current flow to the negative supply voltage source and improved reliability comprises first, second and third series coupled switching devices defining an output and intermediate nodes therebetween respectively for coupling a high voltage source to a reference voltage level. Control terminals of the first and second switching devices are coupled to a first circuit node and a control terminal of the third switching device is coupled to a second circuit node. A fourth switching device is coupled between the lower intermediate node and a negative voltage source, with a control terminal of the fourth switching device being coupled to a third circuit node. In operation, the first circuit node is activated, followed sequentially by the second and third circuit nodes, the second circuit node being deactivated substantially concurrently with the activation of the third circuit node.

Abstract: A read data latch circuit that requires only two phases to execute a data read cycle. The date read lines and data latch lines are precharged and equalized during the data read cycle. A separate phase for equalizing the data latch nodes is eliminated. Rather, the data latch nodes charge share with the previously equalized and precharged data lines. The latch nodes are effectively precharged and equalized, as the capacitance on the data lines is much larger than the capacitance on the data latch nodes.

Abstract: A local write driver circuit for an integrated circuit device memory array which requires only a single write enable signal to couple complimentary data signals between global and local write data lines thereby obviating the need to provide complementary write enable signals as in conventional implementations. By eliminating the need for a second complementary write enable signal line, less on-chip die area is required for the signal path along with a concomitant reduction in power requirements due to the fact that there is one less line which has to switch during a given write cycle.

Abstract: An architecture for a high speed memory circuit having a relatively large number of internal data lines is shown to include global read and write data lines, and power and ground lines extending laterally across the array. The laterally extending lines are preferably within the third layer of metal. Preferably, the only other metal interconnect over the memory arrays is in the first metal layer, which is used to strap the word lines. Sense amp bands extend longitudinally along the borders of each memory cell bank. Local read and write data lines and read and write column select lines extend through the sense amp bands. Power and ground lines also extend through each sense amp band. Preferably, the architecture includes read path circuitry including a local read circuit that selectively isolates the global read data lines from the local read data lines.

Abstract: A reduced skew write timing scheme for memory circuits is disclosed wherein the signals present on the write data lines and the signals present on the write column select lines are clocked on opposite edges of the clock signal. As a result, the timing sensitivity during writing is relaxed. The duty cycle of the clock is preferably close to fifty percent, most preferably within five percent thereof.

Abstract: A reduced capacitance architecture for integrated circuits and particularly for memory integrated circuits is disclosed. The integrated circuit has a plurality of levels including first and second levels. A first signal conductor extends within the first level. A second signal conductor also extends within the first level and is positioned adjacent to and in close proximity with the first signal conductor. The second level is positioned adjacent to the first level and includes a third signal conductor extending within it. The third signal conductor is positioned laterally between the first and second conductors to eliminate vertical parallel plate capacitance.

Abstract: Wordline row redundancy scheme circuitry includes row shift circuitry and row decoder circuitry. If row shift redundancy is not desired, the row shift circuitry applies a first row shift control signal to the row shift control line. If row shift redundancy is desired, the row shift circuit applies a second row shift control signal to the row shift control line. The signal applied to the row shift control line actuates one of first and second electronic switches. Several electronic switches are series-coupled to the first and second electronic switches. The first electronic switch is also series-coupled to a first wordline select line. The second electronic switch is also series-coupled to a second wordline select line adjacent to the first wordline select line. Row address lines are coupled to the several electronic switches to carry row address selection control signals that selectively actuate its electronic switch.