Patents by Inventor Kim Chen

Kim Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240078601
    Abstract: A system, apparatus, method, and non-transitory computer readable medium for performing co-trading changepoint detection may include a server caused to receive a first raw dataset, the first raw dataset including a plurality of transactions for analysis, each transaction of the plurality of transactions associated with a user account of a plurality of user accounts, generate at least one transaction time series based on the first raw dataset, determine changepoints in the first raw dataset by performing changepoint detection analysis on the generated at least one transaction time series, and generate at least one potential fraud alert based on the determined changepoints.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 7, 2024
    Applicant: Charles Schwab & Co., Inc.
    Inventors: Sean Ming-Yin LAW, Kim CHEN
  • Publication number: 20210084956
    Abstract: The present disclosure relates to methods and compositions for weight management and/or hunger control combining a bolus dose of a taste receptor agonist targeting enteroendocrine cells beyond the stomach with food products.
    Type: Application
    Filed: February 22, 2019
    Publication date: March 25, 2021
    Inventors: Kim CHEN, Martin BROWN, Clegg HUBBELL
  • Patent number: 7565635
    Abstract: SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: July 21, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Clinton Chao, Louis Liu, Lewis Chu, Mark Shane Peng, Chao-Shun Hsu, Kim Chen
  • Patent number: 7514775
    Abstract: A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first support structure formed from a second substrate is provided over the first substrate, adjacent to at least one of the first die and the second die. A top surface of the first support structure is substantially coplanar with a top surface of at least one of the first and second dies adjacent to the first support structure. The stacked structure further includes a heat spreader mounted over the second die.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: April 7, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Clinton Chao, Tsorng-Dih Yuan, Hsin-Yu Pan, Kim Chen, Mark Shane Peng, Tjandra Winata Karta
  • Publication number: 20080250182
    Abstract: SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.
    Type: Application
    Filed: April 9, 2007
    Publication date: October 9, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Clinton Chao, Louis Liu, Lewis Chu, Mark Shane Peng, Chao-Shun Hsu, Kim Chen
  • Publication number: 20080083975
    Abstract: A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first support structure formed from a second substrate is provided over the first substrate, adjacent to at least one of the first die and the second die. A top surface of the first support structure is substantially coplanar with a top surface of at least one of the first and second dies adjacent to the first support structure. The stacked structure further includes a heat spreader mounted over the second die.
    Type: Application
    Filed: October 9, 2006
    Publication date: April 10, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Clinton Chao, Tsorng-Dih Yuan, Hsin-Yu Pan, Kim Chen, Mark Shane Peng, Tjandra Winata Karta
  • Publication number: 20080018350
    Abstract: An interposer for converting pitches includes an interconnect structure over the semiconductor substrate, an active circuit formed on the semiconductor substrate, wherein the active circuit is electrically connected to the interconnect structure, a first plurality of pads with a first pitch over the interconnect structure, a second plurality of pads underlying the semiconductor substrate, and a plurality of through-substrate vias in the semiconductor substrate, wherein the first and the second plurality of pads are interconnected through the plurality of through-substrate vias.
    Type: Application
    Filed: September 22, 2006
    Publication date: January 24, 2008
    Inventors: Clinton Chao, Chih-Hsien Chang, John C.Y. Chiang, Mark Shane Peng, Hua-Shu Wu, Kim Chen, Wen-Hung Wu, Tjandra Winada Karta
  • Patent number: 6817884
    Abstract: A multi-I/O-port-41-channel connector includes first and second connectors, in which associated connecting pins and plugholes as well as a fastening device is available to thereby prevent any possible faulty connection and provide a convenient operation for enhanced fastening or detaching of the connectors.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: November 16, 2004
    Inventors: Mao-Hsiung Chen, Kim Chen
  • Patent number: 5690344
    Abstract: An in-line roller skate having an improved sole plate structure includes a boot with an outer sole provided with a plurality of downwardly extending projections. Each projection is provided with a vertically oriented, elongated slot for receiving a bushing of an elastic plastic material for absorbing shock, and at least two pairs of mounting plates for clamping rollers between each pair pivotally-mounted to the corresponding projections. Each pair of mounting pairs secures two rollers at either end thereof. The mounting plates are arranged to be pairs of two and each pair of mounting plates is independently mounted to the projections of the boot. The in-line roller skate has good floor or ground adaptability and shock-absorbing effects.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: November 25, 1997
    Assignee: Playmaker-Co., Ltd.
    Inventor: Kim Chen