Abstract: An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonics and intermodulations typically associated with the frequency conversion process.

Abstract: An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonics and intermodulations typically associated with the frequency conversion process.

Abstract: An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonics and intermodulations typically associated with the frequency conversion process.

Abstract: An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonics and intermodulations typically associated with the frequency conversion process.

Abstract: An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonies and intermodulations typically associated with the frequency conversion process.

Abstract: A system for providing automatic gain control (AGC) comprises a signal path with an RF input, a plurality of power detectors in communication with the signal path, each of the power detectors operable to measure a total broadband power level of a signal in the signal path, each of the power detectors positioned to monitor a point in the signal path corresponding to a change in signal bandwidth, a control system operable to receive from each of the power detectors information associated with the power level and to adjust attenuation in the signal path in response to the information to achieve desired gain control.

Abstract: A device for measuring voltage levels includes a root mean square (RMS) detector. The RMS detector includes a linear multiplier, a log converter, a low-pass filter and a temperature compensator. The linear multiplier multiplies a voltage of an input signal by the voltage of the input signal. The low-pass filter couples to an output of the linear multiplier. The log converter generates a logarithmic signal having a voltage that is logarithmically related to a voltage of an output of the low-pass filter. The temperature compensator adjusts the logarithmic signal based on a temperature of the RMS detector. The RMS detector is capable of determine an RMS voltage level of the input signal.

Abstract: A system for filtering a signal includes a plurality of filter modules coupled in series. Each filter module includes a filter and a variable gain element. Each filter is capable of. receiving an input signal, attenuating a portion of the input signal that is outside a passband associated with the filter, and outputting at least a portion of the input signal that is within the passband associated with the filter. Each variable gain element is capable of receiving a control signal and inducing a gain in an output of the filter based on the control signal.

Abstract: An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonies and intermodulations typically associated with the frequency conversion process.

Abstract: A device for measuring voltage levels includes a root mean square (RMS) detector. The RMS detector includes a linear multiplier, a log converter, a low-pass filter and a temperature compensator. The linear multiplier multiplies a voltage of an input signal by the voltage of the input signal. The low-pass filter couples to an output of the linear multiplier. The log converter generates a logarithmic signal having a voltage that is logarithmically related to a voltage of an output of the low-pass filter. The temperature compensator adjusts the logarithmic signal based on a temperature of the RMS detector. The RMS detector is capable of determine an RMS voltage level of the input signal.

Abstract: A device for measuring voltage levels includes a root mean square (RMS) detector. The RMS detector includes a linear multiplier, a log converter, a low-pass filter and a temperature compensator. The linear multiplier multiplies a voltage of an input signal by the voltage of the input signal. The low-pass filter couples to an output of the linear multiplier. The log converter generates a logarithmic signal having a voltage that is logarithmically related to a voltage of an output of the low-pass filter. The temperature compensator adjusts the logarithmic signal based on a temperature of the RMS detector. The RMS detector is capable of determine an RMS voltage level of the input signal.

Abstract: A system for providing automatic gain control (AGC) comprises a signal path with an RF input, a plurality of power detectors in communication with the signal path, each of the power detectors operable to measure a total broadband power level of a signal in the signal path, each of the power detectors positioned to monitor a point in the signal path corresponding to a change in signal bandwidth, a control system operable to receive from each of the power detectors information associated with the power level and to adjust attenuation in the signal path in response to the information to achieve desired gain control.

Abstract: A filter circuit includes a polyphase filter coupled to a first circuit component and a second circuit component. The first circuit component propagates four input current signals to the polyphase filter. The third and fourth input current signals are substantially one-hundred-eighty degrees out of phase with the first and second input current signals. The polyphase filter receives the input current signals and generates four output current signals that are out of phase with each other. The second circuit component generates first and second output signals using the four output current signals. The first and second output signals are ninety degrees out of phase with each other.

Abstract: A filter circuit includes a polyphase filter coupled to a first circuit component and a second circuit component. The first circuit component propagates four input current signals to the polyphase filter. The third and fourth input current signals are substantially one-hundred-eighty degrees out of phase with the first and second input current signals. The polyphase filter receives the input current signals and generates four output current signals that are out of phase with each other. The second circuit component generates first and second output signals using the four output current signals. The first and second output signals are ninety degrees out of phase with each other.

Abstract: Linearizer circuitry is disclosed for providing control signal outputs to operate a controllable attenuator throughout a relatively large dynamic range while maintaining a relatively consistent return loss. Preferred embodiment linearizer circuitry provides a series control current and a shunt control current for coupling to a PIN diode attenuator, such as may be configured in a ? network or a T network. Preferably, differential pairs are utilized in providing each of the control current outputs.

Abstract: A circuit for establishing a bias current includes a mixer, an amplifier, a bias resistor, a comparator, and a drive circuit. The mixer receives a drive voltage and at least a portion of a bias current. The amplifier is coupled to the mixer and receives at least a portion of the bias current. A bias resistor is coupled to the amplifier at a node and a bias voltage exists at the node. The comparator is coupled to the node and compares the bias voltage with a reference voltage. The comparator further generates an output signal based at least in part upon the comparison. The drive circuit generates the drive voltage in response to the output signal such that the bias voltage substantially equals the reference voltage thereby establishing the bias current.

Abstract: A filter circuit includes a polyphase filter coupled to a first circuit component and a second circuit component. The first circuit component propagates four input current signals to the polyphase filter. The third and fourth input current signals are substantially one-hundred-eighty degrees out of phase with the first and second input current signals. The polyphase filter receives the input current signals and generates four output current signals that are out of phase with each other. The second circuit component generates first and second output signals using the four output current signals. The first and second output signals are ninety degrees out of phase with each other.

Abstract: A circuit for establishing the input impedance of an amplifier includes an amplifier, a circuit component, a first feedback resistor, and a second feedback resistor. The amplifier has an input impedance and is coupled to a load having a load impedance. The circuit component is coupled to the load and shares at least a portion of a bias current with the amplifier. The first feedback resistor is coupled the amplifier and the load, and has a first impedance. The second feedback resistor is coupled to the amplifier and has a second impedance. The input impedance of the amplifier is established based at least in part upon the first impedance and the second impedance.

Abstract: A filter circuit includes a polyphase filter coupled to a first circuit component and a second circuit component. The first circuit component propagates four input current signals to the polyphase filter. The third and fourth input current signals are substantially one-hundred-eighty degrees out of phase with the first and second input current signals. The polyphase filter receives the input current signals and generates four output current signals that are out of phase with each other. The second circuit component generates first and second output signals using the four output current signals. The first and second output signals are ninety degrees out of phase with each other.

Abstract: A circuit for establishing a bias current includes a mixer, an amplifier, a bias resistor, a comparator, and a drive circuit. The mixer receives a drive voltage and at least a portion of a bias current. The amplifier is coupled to the mixer and receives at least a portion of the bias current. A bias resistor is coupled to the amplifier at a node and a bias voltage exists at the node. The comparator is coupled to the node and compares the bias voltage with a reference voltage. The comparator further generates an output signal based at least in part upon the comparison. The drive circuit generates the drive voltage in response to the output signal such that the bias voltage substantially equals the reference voltage thereby establishing the bias current.