Abstract: A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.

Abstract: A three state output circuit which pulls down the output node thereof to a first supply voltage in response to an assert signal, pulls up the output node to a second supply voltage in response to a rescind signal, and then presents a high impedance on the output node immediately after the output node is pulled up to a selected reference voltage.

Abstract: An N-channel MOS high voltage detection circuit generates an output when an input voltage (Vin) exceeds a supply voltage (V.sub.DD) by a desired offset voltage. The crossover detection is delayed by pumping more current into an output producing node via a lower resistance field effect transistor having a gate coupled to the input voltage. The output is finally produced when the effect of this transistor is overcome by a second field effect transistor. Switching characteristics may be sharpened by placing a voltage limiting field effect transistor between Vin and the gate of the low resistance field effect transistor.

Abstract: A compensated Schmitt trigger includes first and second balanced current paths between V.sub.DD and ground for establishing the Schmitt trigger's low and high output respectively. The first path includes a first small enhancement device, a second depletion device and a third enhancement device. The second path includes a fourth enchancement device and said second and third devices. Thus, each path includes two enhancement devices and one depletion device. Process variations in each path will tend to track stabilizing the difference between the low and high switching voltages.

Abstract: An A.C. zero crossover detection circuit compensates for RC phase lead by adding hysteresis to the reference voltage. A reference voltage is applied directly to a first input of a differential amplifier and indirectly through first and second resistor connected field-effect-transistors to a second input of the differential amplifier. An output of the amplifier is coupled to the gate of an MOS switch which, when turned on, reduces the reference voltage by a predetermined amount to compensate for early crossover detection resulting from the phase lead.

Abstract: A differential amplifier, preferably comprised of N-channel MOS devices and having a high ratio of differential gain to common mode gain, has an input stage which receives first and second potentials and amplifies the difference therebetween. Additional amplifying stages each include a depletion input load device having a gate which is coupled to the second potential for balancing the switching points of each additional stage over the common mode range.