Abstract: The system has a predetermined number of semiconductor memory devices with a commonly shared data input/output bus and a processor which controls operations of the predetermined number of semiconductor memory devices with a clock signal, a read/write control signal and a chip selection control signal, wherein the predetermined number of devices respectively comprise: a predetermined number of groups of data input/output drivers for inputting data from outside and outputting the data to outside in response to an internal output control signal; control means for generating a first state of a first control signal in response to a first state of a clock signal of a following cycle when a clock signal, a read/write control signal and a chip selection control signal is inputted from outside to transmit a read command to a previous cycle and when a write or non-selection command is transmitted to a current cycle, and for generating a second state of a second control signal in response to the first state of the clock