Patents by Inventor Kim Hoon

Kim Hoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8741717
    Abstract: Methods for fabricating integrated circuits are provided. One method includes forming first and second FET trenches in an interlayer dielectric material on a semiconductor substrate. The first FET trench is partially filled with a first work function metal to define an inner cavity in the first FET trench. The first work function metal is a N-type work function metal or a P-type work function metal. The N-type work function metal is selected from the group consisting of titanium, tantalum, hafnium, ytterbium silicide, erbium silicide, and titanium silicide. The P-type work function metal is selected from the group consisting of cobalt, nickel, and tungsten silicide. The inner cavity and the second FET trench are filled with a second work function metal to form corresponding metal gate structures. The second work function metal is the other of the N-type work function metal or the P-type work function metal.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 3, 2014
    Assignee: Globalfoundries, Inc.
    Inventor: Kim Hoon
  • Publication number: 20140004693
    Abstract: Methods for fabricating integrated circuits are provided. One method includes forming first and second FET trenches in an interlayer dielectric material on a semiconductor substrate. The first FET trench is partially filled with a first work function metal to define an inner cavity in the first FET trench. The first work function metal is a N-type work function metal or a P-type work function metal. The N-type work function metal is selected from the group consisting of titanium, tantalum, hafnium, ytterbium silicide, erbium silicide, and titanium silicide. The P-type work function metal is selected from the group consisting of cobalt, nickel, and tungsten silicide. The inner cavity and the second FET trench are filled with a second work function metal to form corresponding metal gate structures. The second work function metal is the other of the N-type work function metal or the P-type work function metal.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Kim Hoon
  • Patent number: 6544808
    Abstract: A method is provided for forming quantum holes of nanometer levels. In an ion beam scanner, ions are projected from an ion gun onto a semiconductor substrate. During the projection, ions are focused into an ion beam whose focal point is controlled to determine the diameter of the ion beam, and the ion beam is accelerated. When being incident upon the semiconductor substrate, the ion beam is deflected so as to form a plurality of quantum holes. Also provided is a semiconductor for use in a light emitting device with quantum dots. Impurities are doped onto a semiconductor substrate to form a P-type semiconductor layer on which an undoped, intrinsic semiconductor is grown to a certain thickness. A plurality of quantum holes are provided for the intrinsic semiconductor layer, followed by filling materials smaller in energy band gap than the intrinsic semiconductor in annealed quantum holes through recrystallization growth. Next, an N-type semiconductor layer is overlaid on the quantum hole layer.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: April 8, 2003
    Assignee: NMCTek Co., Ltd.
    Inventor: Kim Hoon
  • Publication number: 20010039066
    Abstract: A method is provided for forming quantum holes of nanometer levels. In an ion beam scanner, ions are projected from an ion gun onto a semiconductor substrate. During the projection, ions are focused into an ion beam whose focal point is controlled to determine the diameter of the ion beam, and the ion beam is accelerated. When being incident upon the semiconductor substrate, the ion beam is deflected so as to form a plurality of quantum holes. Also provided is a semiconductor for use in a light emitting device with quantum dots. Impurities are doped onto a semiconductor substrate to form a P-type semiconductor layer on which an undoped, intrinsic semiconductor is grown to a certain thickness. A plurality of quantum holes are provided for the intrinsic semiconductor layer, followed by filling materials smaller in energy band gap than the intrinsic semiconductor in annealed quantum holes through recrystallization growth. Next, an N-type semiconductor layer is overlaid on the quantum hole layer.
    Type: Application
    Filed: March 2, 2001
    Publication date: November 8, 2001
    Inventor: Kim Hoon