Abstract: A process for reducing device capacitance via inclusion of an air gap in a low dielectric constant (low k), layer, used to fill narrow spaces between metal lines, has been developed. The process features the formation of dual damascene metal lines, comprised with a narrow space between the top portions of the dual damascene metal structures, and a wider space between bottom portions of these same structures. Deposition of a low k layer, using a deposition procedure lacking acceptable conformality properties, results in the narrow space between top portions of the dual damascene metal structures being completely filled with low k layer, while the wider space located between bottom portions of the metal structures remains unfilled. The unfilled portion of the low k layer now features an embedded air gap, resulting in decreased capacitance for the dielectric layer located between metal lines, thus reducing performance degrading RC delays.

Abstract: A method for forming reliable inter-level metal interconnections in semiconductor integrated circuits is described where pillars are formed to connect between different metal layers. A first conductive layer is deposited overlying a substrate. A conductive etch stop layer is deposited overlying the first conductive layer and then patterned to form a mask for the fist conductive layer. This is followed by a deposition of via metal layer overlying the entire surface. A hard mask layer is deposited and patterned to form the mask where via pillars are to be formed. Subsequent anisotropic etching forms pillars in the via met layer and openings in the first conductive layer. An inter-metal dielectric (IMD) layer is deposited covering and filling both the openings in the first conductive layer and in between the via pillars. The surface is then planarized.