Abstract: A controller for a voltage regulator is disclosed. The controller is switchable between first and second modes of operation in which the controller is adapted to control the regulator to operate in switching and linear modes respectively. The controller is further adapted to respond to an input voltage to the voltage regulator to enter a third mode of operation in which the input voltage is coupled directly to an output terminal.

Abstract: An amplifier comprising at least one amplifying element (20a, 25a) and a biasing circuit (32a, 32b) for biasing the or each amplifying element with a bias voltage is disclosed. The biasing circuit (32a, 32b) is adapted to vary the bias voltage such that the or each amplifying element switches between non-switching and switching modes of operation in response to a bias control signal (4) passing through a threshold value.

Abstract: A controller for a voltage regulator is disclosed. The controller is switchable between first and second modes of operation in which the controller is adapted to control the regulator to operate in switching and linear modes respectively. The controller is further adapted to respond to an input voltage to the voltage regulator to enter a third mode of operation in which the input voltage is coupled directly to an output terminal.

Abstract: An amplifier comprising at least one amplifying element (20a, 25a) and a biasing circuit (32a, 32b) for biasing the or each amplifying element with a bias voltage is disclosed. The biasing circuit (32a, 32b) is adapted to vary the bias voltage such that the or each amplifying element switches between non-switching and switching modes of operation in response to a bias control signal (4) passing through a threshold value.

Abstract: Embodiments of the present invention provide a current mode logic circuit, comprising first and second differential switching stages, each stage arranged being arranged to receive a plurality of clock signals, such that the first and second differential switching stages respond to a combination of the plurality of clock signals.

Abstract: There is provided a transceiver comprising a first node for receiving a received signal and transmitting a transmitted signal; a receiver, connected between a first voltage and the first node, for processing the received signal; a transmitter, connected between a second voltage and the first node, for generating the transmitted signal; and a DC voltage controller for selecting a DC component of a voltage of the first node to at least one of: selectively activate at least one of the transmitter and the receiver; and selectively substantially deactivate at least one of the transmitter and receiver.

Abstract: Embodiments of the present invention provide a current mode logic circuit, comprising first and second differential switching stages, each stage arranged being arranged to receive a plurality of clock signals, such that the first and second differential switching stages respond to a combination of the plurality of clock signals.

Abstract: A transconductance control circuit, comprising: a test transconductance circuit for providing an output current from a reference voltage; apparatus for deriving a bias current for the test transconductance circuit from the output current, the bias current including a component that varies with temperature and a component that varies with process; and apparatus for providing the bias current to other transconductance circuits.

Abstract: There is provided a transceiver comprising a first node for receiving a received signal and transmitting a transmitted signal; a receiver, connected between a first voltage and the first node, for processing the received signal; a transmitter, connected between a second voltage and the first node, for generating the transmitted signal; and a DC voltage controller for selecting a DC component of a voltage of the first node to at least one of: selectively activate at least one of the transmitter and the receiver; and selectively substantially deactivate at least one of the transmitter and receiver.

Abstract: A method for estimating the thickness of a desired layer coated on a wafer includes steps of (a) forming a plurality of compared layers having the same composition of the desired layer, (b) measuring the thickness of each of the plurality of compared layers, (c) estimating a factor affecting the thickness due to a solid content in the plurality of compared layers according to the thickness of the plurality of compared layers, and (d) calculating the thickness of the desired layer coated on the wafer by introducing the factor. The desired layer is a photoresist layer formed by a spin coater. The plurality of compared layers in the step (a) are formed at different spinning rates of the spin coater. The factor is estimated by a linear regression method, and the linear regression method is used to obtain an equation representing the relation between the thickness of the plurality of compared layers and each corresponding spinning rate.