Patents by Inventor Kim Meinerth
Kim Meinerth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11503310Abstract: A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write operation with a memory to store the converted image data after completing the conversion process. In another example, a decoding unit is operative to perform a read operation with the memory to retrieve the image data from the memory before initiating the conversion process. In another example, an encoder/decoder unit is operative to perform at least one of: the read operation and the write operation.Type: GrantFiled: October 31, 2018Date of Patent: November 15, 2022Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Lei Zhang, David Glen, Kim A. Meinerth
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Publication number: 20200137403Abstract: A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write operation with a memory to store the converted image data after completing the conversion process. In another example, a decoding unit is operative to perform a read operation with the memory to retrieve the image data from the memory before initiating the conversion process. In another example, an encoder/decoder unit is operative to perform at least one of: the read operation and the write operation.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: LEI ZHANG, DAVID GLEN, KIM A. MEINERTH
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Patent number: 7439986Abstract: A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.Type: GrantFiled: January 2, 2007Date of Patent: October 21, 2008Assignee: Intel CorporationInventors: David W. Watson, Kim A. Meinerth, Indraneel Ghosh, Thomas A. Piazza, Val G. Cook
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Publication number: 20080143695Abstract: A method, apparatus, and system for low power static image display self-refresh are described. In one embodiment, a display controller may operate in a primary display mode or in a low power display mode. The display controller may switch from a primary display mode to a low power display mode when the displayed image has been static for a predetermined time, and may switch from the low power display mode to the primary display mode when the display buffer changes.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: Dale Juenemann, Kim Meinerth
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Publication number: 20070103487Abstract: A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.Type: ApplicationFiled: January 2, 2007Publication date: May 10, 2007Inventors: David Watson, Kim Meinerth, Indraneel Ghosh, Thomas Piazza, Val Cook
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Patent number: 7158147Abstract: A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.Type: GrantFiled: September 4, 2002Date of Patent: January 2, 2007Assignee: Intel CorporationInventors: David W. Watson, Kim A. Meinerth, Indraneel Ghosh, Thomas A. Piazza, Val G. Cook
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Patent number: 7120774Abstract: A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.Type: GrantFiled: September 26, 2003Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Todd M. Witter, Aditya Sreenivas, Kim Meinerth
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Patent number: 6999089Abstract: An overlay video processing system provides an early start to pixel processing for the next overlay scan line. The overlay processor begins processing the next overlay scan line while still displaying the current scan line. A FIFO buffer is used to provide the overlay video data to the display. When the buffer provides a predetermined amount of data to the current overlay scan line, the buffer begins to load the data for the next overlay scan line. In one embodiment, the buffer may begin loading data for the next overlay scan line when approximately half the current overlay scan line is displayed.Type: GrantFiled: March 30, 2000Date of Patent: February 14, 2006Assignee: Intel CorporationInventors: Fong-Shek Lam, Kim A. Meinerth
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Publication number: 20050044334Abstract: A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.Type: ApplicationFiled: September 26, 2003Publication date: February 24, 2005Inventors: Todd Witter, Aditya Sreenivas, Kim Meinerth
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Patent number: 6629253Abstract: A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.Type: GrantFiled: December 30, 1999Date of Patent: September 30, 2003Assignee: Intel CorporationInventors: Todd M. Witter, Aditya Sreenivas, Kim Meinerth
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Patent number: 6597373Abstract: A display controller that includes a controller adapted to receive images selectable in real-time to any of a two or more of differing scanning resolutions, adapted to receive information regarding a fixed scanning resolution of a display device, and adapted to generate image borders taking into consideration the information of the fixed scanning resolution and a currently selected one of the two or more differing scanning resolutions, in order to control placement of the images on the display device.Type: GrantFiled: January 7, 2000Date of Patent: July 22, 2003Assignee: Intel CorporationInventors: Ashutosh Singla, Richard W. Jensen, Kim A. Meinerth, Paul A. Jolly
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Publication number: 20030001861Abstract: A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.Type: ApplicationFiled: September 4, 2002Publication date: January 2, 2003Inventors: David W. Watson, Kim A. Meinerth, Indraneel Ghosh, Thomas A. Piazza, Val G. Cook
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Patent number: 6466226Abstract: A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.Type: GrantFiled: January 10, 2000Date of Patent: October 15, 2002Assignee: Intel CorporationInventors: David W. Watson, Kim A. Meinerth, Indraneel Ghosh, Thomas A. Piazza, Val G. Cook
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Patent number: 6199149Abstract: A method for controlling processing of overlay requests is disclosed. The method comprises the step of disabling an overlay request to a memory. The overlay request to system memory has expedited processing priority over requests to a system memory by other devices. The overlay request is disabled for a predetermined time period and enabled after the predetermined time period has elapsed.Type: GrantFiled: January 30, 1998Date of Patent: March 6, 2001Assignee: Intel CorporationInventors: Kim A. Meinerth, Aditya Sreenivas, Krishnan Sreenivas
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Patent number: 6141023Abstract: An apparatus for an efficient display flip is disclosed. The apparatus has a computer readable medium having a graphics driver. The execution of the graphics driver is configured to generate instructions for checking status of a graphics device to determine whether the graphics device is ready to display a next frame data on a display device. The graphics device is coupled to a system memory. The graphics device is configured to forwarding a display flip status to the system memory for access by the graphics driver in response to the instructions.Type: GrantFiled: January 30, 1998Date of Patent: October 31, 2000Assignee: Intel CorporationInventors: Kim A. Meinerth, Aditya Sreenivas, Krishnan Sreenivas, John A. Carey
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Patent number: 6124865Abstract: A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry into, or displacement from, the CPU cache tag store is also entered into, or displaced from, the second cache tag store.Type: GrantFiled: December 19, 1995Date of Patent: September 26, 2000Assignee: Digital Equipment CorporationInventors: Kim Meinerth, John Kirk, George Lord
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Patent number: 6097402Abstract: A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.Type: GrantFiled: February 10, 1998Date of Patent: August 1, 2000Assignee: Intel CorporationInventors: Colyn Case, Brian K. Langendorf, George R. Hayek, Kim A. Meinerth
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Patent number: 6091431Abstract: A graphics device implemented in accordance with one embodiment of the invention includes a first request path to a local memory interface for low-priority read transactions and a second request path to the local memory interface for low-priority write transactions. The second request path is also used for read transactions received over a system bus. The graphics device further includes an arbiter that arbitrates between the first request path and the second request path, with the second request path having a higher priority than the first request path.Type: GrantFiled: December 18, 1997Date of Patent: July 18, 2000Assignee: Intel CorporationInventors: Alankar Saxena, Aditya Sreenvas, Kim A. Meinerth
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Patent number: 6078339Abstract: A method for mutual exclusion of drawing engine execution on a graphics device is disclosed. The method checks a busy signal of an executing drawing engine. The executing drawing engine is one of a plurality of drawing engines of the graphics device and the only drawing engine executing out of the plurality of drawing engines. The method forwards a graphics instruction and associated data packet to a next drawing engine to execute after the executing drawing engine has completed execution. The next drawing engine to execute is one of the plurality of drawing engines.Type: GrantFiled: February 10, 1998Date of Patent: June 20, 2000Assignee: Intel CorporationInventors: Kim A. Meinerth, Aditya Sreenivas, Krishnan Sreenivas
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Patent number: 6025855Abstract: A method for communicating graphics device status information to a graphics driver. Status of a graphics device is checked to determine whether the graphics device is ready to process a next instruction. A location in cacheable memory accessible to a graphics driver is updated with the status. The graphics driver reads the status to determine when to generate the next instruction for processing by the graphics data. A first instruction to be forwarded to the graphics device is generated. A status in an operating register in the graphics device is updated indicating that an event is being monitored. The updating is performed in response to receipt of the first instruction by the graphics device. The status is written to a second cacheable location in system memory accessible to the graphics driver. A second instruction is generated by the graphics driver to provide a predetermined address and instruction completion data to the graphics device.Type: GrantFiled: February 10, 1998Date of Patent: February 15, 2000Assignee: Intel CorporationInventors: Kim A. Meinerth, Aditya Sreenivas, Krishnan Sreenivas